/* Set up and initialize clocking prior to call to main */
void Board_SetupClocking(void)
{
int i;
Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
Divide rate is based on CPU speed and speed of SPI FLASH part. */
#if (MAX_CLOCK_FREQ > 180000000)
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
}
/* Setup system clocking */
STATIC void SystemSetupClocking(void)
{
int i;
/* Switch main system clocking to crystal */
Chip_Clock_EnableCrystal();
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
/* SPIFI pin setup is done prior to setting up system clocking */
for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
Chip_SCU_PinMuxSet(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
spifipinmuxing[i].modefunc);
}
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
Divide rate is based on CPU speed and speed of SPI FLASH part. */
#if (MAX_CLOCK_FREQ > 180000000)
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
/* Attach main PLL clock to divider C with a divider of 2 */
Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
/* Setup default USB PLL state for a 480MHz output and attach */
Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
/* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
chained to make a divide by 8 function. Connect the output of
divider D to the USB1 base clock. */
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
/* Setup default audio PLL state for a FIXME output */
// Chip_Clock_SetupPLL(CGU_AUDIO_PLL, &audioPLLSetup); // FIXME
}
/**
* Post wake up initialisation function
*/
static void PMC_Post_Wakeup(uint8_t buffer)
{
int i;
#ifdef BOARD_KEIL_MCB_18574357
/* Setup FLASH acceleration to target clock rate prior to clock switch */
Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
#endif
/* Reinitialise Clocks */
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
/* Restore the base clock states */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
Divide rate is based on CPU speed and speed of SPI FLASH part. */
#if (MAX_CLOCK_FREQ > 180000000)
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
/* Attach main PLL clock to divider C with a divider of 2 */
Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
/* Re-Initialize debug UART
* � 115200bps
* � 8 data bit
* � No parity
* � 1 stop bit
* � No flow control
*/
DEBUGINIT();
#ifndef BOARD_NGX_XPLORER_18304330
/* SDRAM in NORMAL mode, only for Keil & Hitex boards */
LPC_EMC->DYNAMICCONTROL &= ~(1 << 2);
while (LPC_EMC->STATUS & (1 << 2)) {}
#endif
}
void Chip_USB1_Init(void)
{
/* Setup and enable the PLL */
Chip_USB_PllSetup();
/* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
chained to make a divide by 8 function. Connect the output of
divider D to the USB1 base clock. */
Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
/* enable USB main clock */
Chip_Clock_EnableBaseClock(CLK_BASE_USB1);
Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);
/* enable USB1_DP and USB1_DN on chip FS phy.*/
LPC_SCU->SFSUSB = 0x12;
}
/* Setup system clocking */
STATIC void SystemSetupClocking(void)
{
int i;
/* Switch main system clocking to crystal */
Chip_Clock_EnableCrystal();
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false);
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
/* Setup PLL for maximum clock */
Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ);
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}
/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
/* SPIFI pin setup is done prior to setting up system clocking */
for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) {
Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum,
spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum);
}
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
Divide rate is based on CPU speed and speed of SPI FLASH part. */
#if (MAX_CLOCK_FREQ > 180000000)
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
}
/**
* @brief Main entry point
* @return Nothing
*/
int main(void)
{
uint32_t SCT_FRQ;
Board_Init();
/* Initialize SCT */
Chip_SCT_Init(LPC_SCT);
LPC_SCU->SFSCLK[3] = SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC1; /* function 1; CGU clk out, pull up */
/* Attach IRC clock to divider B with a divider of 16 */
Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IRC, 16);
/* Route divider B output to Clock output base clock and enable base out clock */
Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_IDIVB, true, false);
/* Configure SCT pins */
SCT_PinsConfigure();
SCT_FRQ = Chip_Clock_GetRate(CLK_MX_SCT);
DEBUGOUT("SCT_FRQ: %d\r\n", SCT_FRQ);
Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_HALT_L | SCT_CTRL_PRE_L(256 - 1)
| SCT_CTRL_HALT_H | SCT_CTRL_CLRCTR_H | SCT_CTRL_PRE_H(256 - 1),
ENABLE);
/* Now use the FSM code to configure the state machine */
sct_fsm_init();
/* initialize random seed: */
srand(0x5EED);
/* 12000000 / 256 / 16 = 2929 Hz
* 65535 / 2929 =~ 22 */
/* generate a random delay from 1 to 22 seconds */
delay = (rand() % 22 + 1) * 2929;
NVIC_ClearPendingIRQ(SCT_IRQn);
NVIC_EnableIRQ(SCT_IRQn);
/* Start the SCT */
Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_STOP_L | SCT_CTRL_HALT_L | SCT_CTRL_STOP_H | SCT_CTRL_HALT_H, DISABLE);
while (1) {
__WFI();
}
}
platform_result_t platform_spifi_init( const platform_spifi_t* spifi )
{
uint32_t spifiBaseClockRate;
uint32_t maxSpifiClock;
/*
if( spi_ptr->semaphore_is_inited == WICED_FALSE )
{
host_rtos_init_semaphore( &spi_ptr->in_use_semaphore );
spi_ptr->semaphore_is_inited = WICED_TRUE;
}
else
{
host_rtos_get_semaphore( &spi_ptr->in_use_semaphore, NEVER_TIMEOUT, WICED_FALSE );
}
*/
/* Mux the port and pin to direct it to SPIFI */
platform_pin_set_alternate_function( &spifi->clock );
platform_pin_set_alternate_function( &spifi->miso );
platform_pin_set_alternate_function( &spifi->mosi );
platform_pin_set_alternate_function( &spifi->sio2 );
platform_pin_set_alternate_function( &spifi->sio3 );
platform_pin_set_alternate_function( &spifi->cs );
/* SPIFI base clock will be based on the main PLL rate and a divider */
spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL);
/* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows
* higher divider values up to 256 maximum)
*/
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1));
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
/* Initialize LPCSPIFILIB library, reset the interface */
spifiInit( ( uint32_t )spifi->spifi_base, true);
/* register support for the family(s) we may want to work with */
spifiRegisterFamily( SPIFI_REG_FAMILY_MacronixMX25L );
/* Initialize and detect a device and get device context */
spifi_handle = spifiInitDevice( &lmem, sizeof(lmem), ( uint32_t ) spifi->spifi_base, SPIFLASH_BASE_ADDRESS );
/* Get some info needed for the application */
maxSpifiClock = spifiDevGetInfo(spifi_handle, SPIFI_INFO_MAXCLOCK);
/* Setup SPIFI clock to at the maximum interface rate the detected device
can use. This should be done after device init. */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1));
/* start by unlocking the device */
if (spifiDevUnlockDevice(spifi_handle) != SPIFI_ERR_NONE) {
return WICED_ERROR;
}
/* Enable quad. If not supported it will be ignored */
spifiDevSetOpts(spifi_handle, SPIFI_OPT_USE_QUAD, true);
/* Enter memMode */
spifiDevSetMemMode(spifi_handle, true);
/* Just a test */
maxSpifiClock = *( (uint32_t *)SPIFLASH_BASE_ADDRESS );
return spifi_handle == NULL ? WICED_ERROR : WICED_SUCCESS;
}
static void RunExample(void)
{
uint32_t spifiBaseClockRate;
uint32_t maxSpifiClock;
uint16_t libVersion;
SPIFI_HANDLE_T *pSpifi;
/* Report the library version to start with */
libVersion = spifiGetLibVersion();
DEBUGOUT("\r\n\r\nSPIFI Lib Version %02d%02d\r\n", ((libVersion >> 8) & 0xff), (libVersion & 0xff));
/* set the blink rate to 1/2 second while testing */
test_suiteSetErrorBlinkRate(500);
/* Setup SPIFI FLASH pin muxing (QUAD) */
Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T));
/* SPIFI base clock will be based on the main PLL rate and a divider */
spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL);
/* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows
higher divider values up to 256 maximum) */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1));
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
DEBUGOUT("SPIFI clock rate %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE));
/* initialize and get a handle to the spifi lib */
pSpifi = initializeSpifi();
/* Get some info needed for the application */
maxSpifiClock = spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXCLOCK);
/* Get info */
DEBUGOUT("Device family = %s\r\n", spifiDevGetFamilyName(pSpifi));
DEBUGOUT("Capabilities = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_CAPS));
DEBUGOUT("Device size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_DEVSIZE));
DEBUGOUT("Max Clock Rate = %d\r\n", maxSpifiClock);
DEBUGOUT("Erase blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKS));
DEBUGOUT("Erase block size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKSIZE));
DEBUGOUT("Erase sub-blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKS));
DEBUGOUT("Erase sub-blocksize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKSIZE));
DEBUGOUT("Write page size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_PAGESIZE));
DEBUGOUT("Max single readsize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXREADSIZE));
DEBUGOUT("Current dev status = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_STATUS));
DEBUGOUT("Current options = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_OPTIONS));
/* Setup SPIFI clock to at the maximum interface rate the detected device
can use. This should be done after device init. */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1));
DEBUGOUT("SPIFI final Rate = %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE));
DEBUGOUT("\r\n");
/* Test the helper functions first */
test_suiteLibHelperBattery(pSpifi);
/* Now test the erase functions first in block mode, then in address mode */
test_suiteLibEraseBattery(pSpifi, false);
test_suiteLibEraseBattery(pSpifi, true);
/* test data integrity */
test_suiteDataBattery(pSpifi, false, false);
test_suiteDataBattery(pSpifi, true, false);
test_suiteDataBattery(pSpifi, true, true);
/* Done, de-init will enter memory mode */
spifiDevDeInit(pSpifi);
/* Indicate success */
DEBUGOUT("Complete.\r\n");
test_suiteSetErrorBlinkRate(0);
while (1) {
__WFI();
}
}
