Exemplo n.º 1
0
/* Set/Clear SCT control register */
void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena)
{
	if (ena == ENABLE) {
		Chip_SCT_SetControl(pSCT, value);
	}
	else {
		Chip_SCT_ClearControl(pSCT, value);
	}
}
Exemplo n.º 2
0
int execute_SCT_match_test( LPC_SCT_T *pSCT, CounterWidth counter_width, CHIP_SCT_MATCH_REG_T match_register,
    uint32_t match_count, SCTClock sct_clock, SCTInputEdge sct_input_edge) {

  uint32_t cfg = 0, evt_ctrl = 0;
  int i;

  /* Custom Initialization */
  Chip_SCT_Init(pSCT);

  switch (counter_width) {
    case kCounterWidth16Bits:
      cfg |= SCT_CONFIG_16BIT_COUNTER;
      break;
    case kCounterWidth32Bits:
      cfg |= SCT_CONFIG_32BIT_COUNTER;
      break;
  }

  switch (sct_clock) {
    case kSystemClock:
      cfg |= SCT_CONFIG_CLKMODE_SYSCLK;
      break;
    case kPrescaledSystemClock:
      cfg |= SCT_CONFIG_CLKMODE_PRESCALED_SYSCLK;
      break;
    case kSCTInput:
      cfg |= SCT_CONFIG_CLKMODE_SCT_INPUT;
      break;
    case kPrescaledSCTInput:
      cfg |= SCT_CONFIG_CLKMODE_PRESCALED_SCT_INPUT;
      break;
  }

  if ((sct_clock == kSCTInput) || (sct_clock == kPrescaledSCTInput)) {
    switch (sct_input_edge) {
      case kRisingInput0:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_0;
        break;
      case kFallingInput0:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_0;
        break;
      case kRisingInput1:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_1;
        break;
      case kFallingInput1:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_1;
        break;
      case kRisingInput2:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_2;
        break;
      case kFallingInput2:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_2;
        break;
      case kRisingInput3:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_3;
        break;
      case kFallingInput3:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_3;
        break;
      case kRisingInput4:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_4;
        break;
      case kFallingInput4:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_4;
        break;
      case kRisingInput5:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_5;
        break;
      case kFallingInput5:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_5;
        break;
      case kRisingInput6:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_6;
        break;
      case kFallingInput6:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_6;
        break;
      case kRisingInput7:
        cfg |= SCT_CONFIG_CKSEL_RISING_IN_7;
        break;
      case kFallingInput7:
        cfg |= SCT_CONFIG_CKSEL_FALLING_IN_7;
        break;
    }
  }

  Chip_SCT_Config(pSCT, cfg);

  /* The match/capture REGMODE defaults to match mode */

  /* Set the match count */
  Chip_SCT_SetMatchCount(pSCT, match_register, match_count);

  /* Set the match reload value */
  Chip_SCT_SetMatchReload(pSCT, match_register, match_count);

  /* Setup so that a match in the match_register when in State 0 causes Event 0.
   * Setup so Event 0 causes a Limit condition
   */
  evt_ctrl |= SCT_EV_CTRL_MATCHSEL(match_register) | SCT_EV_CTRL_HEVENT_L |
          SCT_EV_CTRL_COMBMODE_MATCH;
  Chip_SCT_EventControl(pSCT, 0, evt_ctrl);
  Chip_SCT_EventStateMask(pSCT, 0, (1UL << 0));
  Chip_SCT_Limit(pSCT, (1UL << 0));

  /* Setup to toggle all outputs on match */
  for (i = 0; i < CONFIG_SCT_nOU; i++) {
    LPC_SCT->OUT[i].SET = (1UL << 0);
    LPC_SCT->OUT[i].CLR = (1UL << 0);
    Chip_SCT_SetConflictResolution(LPC_SCT, i, 0x3);
  }

  /* Enable an Interrupt on the Match Event */
  Chip_SCT_EnableEventInt(pSCT, SCT_EVT_0);

  /* Enable the IRQ for the SCT */
  NVIC_EnableIRQ(SCT_IRQn);

  /* Start the counter */
  if (counter_width == kCounterWidth32Bits) {
    Chip_SCT_ClearControl(pSCT, SCT_CTRL_HALT_L);
  }
	else {
    // TODO deal with 16 bit counter mode
  }

  return 0;
}