/** SSP macro: write 1 bytes to FIFO buffer */
STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFF);
}
xf_setup->tx_cnt++;
}
void
spi_xfer_wr_byte(spi_desc_t *desc, uint8_t wdata)
{
/* Wait for TXFIFO to have space */
while (Chip_SSP_GetStatus(desc->spi_dev, SSP_STAT_TNF) != SET)
;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(desc->spi_dev, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(desc->spi_dev);
--desc->n_outstanding;
}
Chip_SSP_SendFrame(desc->spi_dev, wdata);
++desc->n_outstanding;
}
void
spi_xfer_rw(spi_desc_t *desc, uint8_t *wdata, int wlen, uint8_t *rdata, int rlen)
{
int i;
int len = max(wlen, rlen);
uint8_t last_wdata = wdata[wlen-1];
uint8_t rd_byte;
/* Drain any outstanding request */
spi_xfer_wait(desc);
for (i = 0; i < len; i++) {
/* Wait for TXFIFO to have space */
while (Chip_SSP_GetStatus(desc->spi_dev, SSP_STAT_TNF) != SET)
;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(desc->spi_dev, SSP_STAT_RNE)) {
rd_byte = Chip_SSP_ReceiveFrame(desc->spi_dev);
--desc->n_outstanding;
if (rlen > 0) {
*rdata++ = rd_byte;
--rlen;
}
}
Chip_SSP_SendFrame(desc->spi_dev, (i < wlen) ? *wdata++ : last_wdata);
++desc->n_outstanding;
}
/* Wait for TXFIFO to drain */
while (Chip_SSP_GetStatus(desc->spi_dev, SSP_STAT_TFE) != SET)
;
while (rlen > 0) {
if (Chip_SSP_GetStatus(desc->spi_dev, SSP_STAT_RNE) == SET) {
rd_byte = Chip_SSP_ReceiveFrame(desc->spi_dev);
--desc->n_outstanding;
*rdata++ = rd_byte;
--rlen;
}
}
}
int main(void) {
#if defined (__USE_LPCOPEN)
#if !defined(NO_BOARD_LIB)
SystemCoreClockUpdate(); /* Read clock settings and update SystemCoreClock variable
* Set up and initialize all required blocks and
* functions related to the board hardware */
Board_Init();
#endif
#endif
/* SSP initialization */
Board_SSP_Init(LPC_SSP); /* enable */
Chip_SSP_Init(LPC_SSP);
Chip_Clock_SetSSP0ClockDiv(18);
/* define peripherals options */
ssp_format.frameFormat = SSP_FRAMEFORMAT_SPI;
ssp_format.bits = SSP_DATA_BITS;
ssp_format.clockMode = SSP_CLOCK_MODE0;
/* set parameters to peripherals SSP0 */
Chip_SSP_SetFormat(LPC_SSP, ssp_format.bits, ssp_format.frameFormat, ssp_format.clockMode);
/* Set the SSP operating modes, master or slave */
Chip_SSP_SetMaster(LPC_SSP, SSP_MODE_TEST);
/* Enable SSP operation */
Chip_SSP_Enable(LPC_SSP);
Chip_SSP_SendFrame(LPC_SSP, flipByte(0xB0));
//Chip_SSP_SendFrame(LPC_SSP, 0b00001101); // load address 0
//_delay_ms(1);
Chip_SSP_SendFrame(LPC_SSP, 0b01110000); // load D letter
//_delay_ms(1);
Chip_SSP_SendFrame(LPC_SSP, 0b11001100);
//_delay_ms(1);
Chip_SSP_SendFrame(LPC_SSP, 0b10101010);
//_delay_ms(1);
Chip_SSP_SendFrame(LPC_SSP, 0b10011110);
//_delay_ms(1);
Chip_SSP_SendFrame(LPC_SSP, 0b01110001);
return 0 ;
}
/* SSP Polling Read in blocking mode */
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
{
uint32_t rx_cnt = 0, tx_cnt = 0;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
uint16_t *rdata16;
rdata16 = (uint16_t *) buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFFFF); /* just send dummy data */
tx_cnt += 2;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata16 = Chip_SSP_ReceiveFrame(pSSP);
rdata16++;
rx_cnt += 2;
}
}
}
else {
uint8_t *rdata8;
rdata8 = buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFF); /* just send dummy data */
tx_cnt++;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata8 = Chip_SSP_ReceiveFrame(pSSP);
rdata8++;
rx_cnt++;
}
}
}
return rx_cnt;
}
