//********************************************************************************
// Function Name : SelectGySleep
// Retun Value : NON
// Argment Value : mode
// Explanation : Select Gyro mode Function
// History : First edition 2010.12.27 Y.Shigeoka
//********************************************************************************
void SelectGySleep( unsigned char UcSelMode )
{
unsigned char UcRamIni ;
unsigned char UcGrini ;
if(UcSelMode == ON)
{
RegWriteA( GEQON, 0x00 ) ; // 0x0100 GYRO Equalizer OFF
RegWriteA( GRSEL, 0x01 ) ; /* 0x0380 Set Command Mode */
RegReadA( GRINI , &UcGrini ); // 0x0381 [ PARA_REG | AXIS7EN | AXIS4EN | - ][ LSBF | SLOWMODE | I2CMODE | - ]
RegWriteA( GRINI, ( UcGrini | SLOWMODE) ); // 0x0381 [ PARA_REG | AXIS7EN | AXIS4EN | - ][ LSBF | SLOWMODE | I2CMODE | - ]
RegWriteA( GRADR0, 0x6B ) ; /* 0x0383 Set Write Command */
RegWriteA( GRACC, 0x02 ) ; /* 0x0382 Set Read Trigger ON */
AccWit( 0x10 ) ; /* Digital Gyro busy wait */
RegReadA( GRADT0H, &UcRamIni ) ; /* 0x0390 */
UcRamIni |= 0x40 ; /* Set Sleep bit */
RegWriteA( GRADR0, 0x6B ) ; /* 0x0383 Set Write Command */
RegWriteA( GSETDT, UcRamIni ) ; /* 0x038A Set Write Data(Sleep ON) */
RegWriteA( GRACC, 0x10 ) ; /* 0x0382 Set Trigger ON */
AccWit( 0x10 ) ; /* Digital Gyro busy wait */
}
else
{
RegWriteA( GRADR0, 0x6B ) ; /* 0x0383 Set Write Command */
RegWriteA( GRACC, 0x02 ) ; /* 0x0382 Set Read Trigger ON */
AccWit( 0x10 ) ; /* Digital Gyro busy wait */
RegReadA( GRADT0H, &UcRamIni ) ; /* 0x0390 */
UcRamIni &= ~0x40 ; /* Clear Sleep bit */
RegWriteA( GSETDT, UcRamIni ) ; // 0x038A Set Write Data(Sleep OFF)
RegWriteA( GRACC, 0x10 ) ; /* 0x0382 Set Trigger ON */
AccWit( 0x10 ) ; /* Digital Gyro busy wait */
RegReadA( GRINI , &UcGrini ); // 0x0381 [ PARA_REG | AXIS7EN | AXIS4EN | - ][ LSBF | SLOWMODE | I2CMODE | - ]
RegWriteA( GRINI, ( UcGrini & ~SLOWMODE) ); // 0x0381 [ PARA_REG | AXIS7EN | AXIS4EN | - ][ LSBF | SLOWMODE | I2CMODE | - ]
GyOutSignal( ) ; /* Select Gyro output signal */
WitTim( 50 ) ; // 50ms wait
RegWriteA( GEQON, 0x01 ) ; // 0x0100 GYRO Equalizer ON
ClrGyr( 0x06 , CLR_GYR_DLY_RAM );
}
}
int32_t HtcActOisBinder_act_set_ois_mode(int ois_mode)
{
int32_t rc = 0;
pr_info("[OIS] %s ois_mode=%d\n", __func__, ois_mode);
g_ois_mode = ois_mode;
RtnCen(0);
if (ois_mode != 0) {
ClrGyr(0x06, CLR_GYR_DLY_RAM);
OisEna();
SetGcf(5);
}
return rc;
}
void IniGyr( void )
{
/*Initialize Gyro RAM*/
ClrGyr( 0x00 , CLR_GYR_ALL_RAM );
/*Gyro Filter Setting*/
RegWriteA( GEQSW , 0x11 ); // 0x0101 [ - | - | Sine_In | AD_In ][ - | - | - | T-Filter_Out ]
RegWriteA( GSHAKEON , 0x01 ); // 0x0102 [ - | - | - | - ][ - | - | - | CmShakeOn ]
RegWriteA( GSHTON , 0x00 ); // 0x0104 [ - | - | - | CmSht2PanOff ][ - | - | CmShtOpe(1:0) ]
// CmShtOpe[1:0] 00: シャッターOFF, 01: シャッターON, 1x:外部制御
RegWriteA( G2NDCEFON1,0x00 ); // 0x0107 [ - | - | - | gxistp ][ gxlens | gxzoom | gxgain | gxgyro ]
RegWriteA( G2NDCEFON0,0x00 ); // 0x0106 [ L4 | L3 | L2 | L1 ][ H2 | H1 | I2 | I1 ]
RegWriteA( GADMEANON, 0x00 ); // 0x0113 [ - | - | - | - ][ - | - | - | CmAdMeanOn ]
RegWriteA( GVREFADD , 0x14 ); // 0x0114 センター戻しを行う遅延RAMのアドレス下位6ビット (default 0x14 = GXH1Z2/GYH1Z2)
RegWriteA( GSHTMOD , 0x0E ); // 0x0115 Shutter Hold mode
RegWriteA( GLMT3MOD , 0x00 ); // 0x0116 [ - | - | - | - ][ - | - | - | CmLmt3Mod ]
// CmLmt3Mod 0: 通常リミッター動作, 1: 円の半径リミッター動作
RegWriteA( GLMT3SEL , 0x00 ); // 0x0117 [ - | - | - | - ][ - | - | - | CmLmt3Sel ]
// CmLmt3Sel 0: gxlmt3H0/gylmt3H0を使用, 1: gxlmt3H1/gylmt3H1を使用
RegWriteA( GGADON , 0x01 ); // 0x011C [ - | - | - | CmSht2PanOff ][ - | - | CmGadOn(1:0) ]
// CmGadOn[1] 0: CmDwmSmpの設定でサンプリング, 1: 毎Fs周期でサンプリング
// CmGadOn[0] 0: Analog Gyro使用, 1: Digital Gyro使用
RegWriteA( GGADSMP1 , 0x01 ); // 0x011E Digital GyroのAD変換確定時間を設定
RegWriteA( GGADSMP0 , 0x00 ); // 0x011D
RegWriteA( GGADSMPT , 0x0E); // 0x011F X軸とY軸のみ取得する場合、0x0Eに設定
// 1Fsで4軸取得する場合、0x2Dに設定
// 2FS以上で4軸取得する場合、0x1Eに設定
/*Gyro Filter Down Sampling*/
RegWriteA( GDWNSMP1 , 0x00 ); // 0x0110 For overall filter
RegWriteA( GDWNSMP2 , 0x00 ); // 0x0111 For H1 fitler
RegWriteA( GDWNSMP3 , 0x00 ); // 0x0112 For T filter
/*Gyro Filter Floating Point Value Limits*/
RegWriteA( GEXPLMTH , 0x81 ); // 0x019C
RegWriteA( GEXPLMTL , 0x5A ); // 0x019D
// Limiter
RamWrite32A( gxlmt1L, 0x00000000 ) ; // 0x18B0
RamWrite32A( gxlmt1H, 0x3F800000 ) ; // 0x18B1 1.0
RamWrite32A( gylmt1L, 0x00000000 ) ; // 0x19B0
RamWrite32A( gylmt1H, 0x3F800000 ) ; // 0x19B1 1.0
RamWrite32A( gxlmt2L, 0x00000000 ) ; // 0x18B2
RamWrite32A( gxlmt2H, 0x3F800000 ) ; // 0x18B3
RamWrite32A( gylmt2L, 0x00000000 ) ; // 0x19B2
RamWrite32A( gylmt2H, 0x3F800000 ) ; // 0x19B3
RamWrite32A( gxlmt4SL, GYRO_LMT4L ) ; // 0x1808
RamWrite32A( gxlmt4SH, GYRO_LMT4H ) ; // 0x1809
RamWrite32A( gylmt4SL, GYRO_LMT4L ) ; // 0x1908
RamWrite32A( gylmt4SH, GYRO_LMT4H ) ; // 0x1909
// Limiter3
RamWrite32A( gxlmt3H0, 0x3F333333 ) ; // 0x18B4 0.7
RamWrite32A( gylmt3H0, 0x3F333333 ) ; // 0x19B4 0.7
RamWrite32A( gxlmt3H1, 0x3F333333 ) ; // 0x18B5 0.7
RamWrite32A( gylmt3H1, 0x3F333333 ) ; // 0x19B5 0.7
// Monitor Circuit
RegWriteA( GDLYMON10, 0xF5 ) ; // 0x0184
RegWriteA( GDLYMON11, 0x01 ) ; // 0x0185
RegWriteA( GDLYMON20, 0xF5 ) ; // 0x0186
RegWriteA( GDLYMON21, 0x00 ) ; // 0x0187
RamWrite32A( gdm1g, 0x3F800000 ) ; // 0x18AC
RamWrite32A( gdm2g, 0x3F800000 ) ; // 0x19AC
RegWriteA( GDLYMON30, 0xF5 ) ; // 0x0188
RegWriteA( GDLYMON31, 0x01 ) ; // 0x0189
RegWriteA( GDLYMON40, 0xF5 ) ; // 0x018A
RegWriteA( GDLYMON41, 0x00 ) ; // 0x018B
RamWrite32A( gdm3g, 0x3F800000 ) ; // 0x18AD
RamWrite32A( gdm4g, 0x3F800000 ) ; // 0x19AD
RegWriteA( GPINMON3, 0x3C ) ; // 0x0182
RegWriteA( GPINMON4, 0x38 ) ; // 0x0183
/*Data Pass Setting*/
RegWriteA( GDPI1ADD1, 0x01 ); // 0x0171 Data Pass 1 Input
RegWriteA( GDPI1ADD0, 0xC0 ); // 0x0170
RegWriteA( GDPO1ADD1, 0x01 ); // 0x0173 Data Pass 1 Output
RegWriteA( GDPO1ADD0, 0xC0 ); // 0x0172
RegWriteA( GDPI2ADD1, 0x00 ); // 0x0175 Data Pass 2 Input
RegWriteA( GDPI2ADD0, 0xC0 ); // 0x0174
RegWriteA( GDPO2ADD1, 0x00 ); // 0x0177 Data Pass 2 Output
RegWriteA( GDPO2ADD0, 0xC0 ); // 0x0176
/*Input Sine Wave or AD value*/
RegWriteA( GSINTST , 0x00 ); // 0x018F [ - | - | - | CmSinTst_X ][ - | - | - | CmSinTst_Y ]
// CmSinTst_X/Y 0: AD値を使用, 1: Sin波を使用
/* Pan/Tilt parameter */
RegWriteA( GPANADDA, 0x14 ); // 0x0130
RegWriteA( GPANADDB, 0x0E ); // 0x0131
//Threshold
RamWrite32A( SttxHis, 0x00000000 ); // 0x183F
RamWrite32A( SttyHis, 0x00000000 ); // 0x193F
RamWrite32A( SttxaL, 0x00000000 ); // 0x18AE
RamWrite32A( SttxbL, 0x00000000 ); // 0x18BE
RamWrite32A( Sttx12aM, GYRA12_MID ); // 0x184F
RamWrite32A( Sttx12aH, GYRA12_HGH ); // 0x185F
RamWrite32A( Sttx12bM, GYRB12_MID ); // 0x186F
RamWrite32A( Sttx12bH, GYRB12_HGH ); // 0x187F
RamWrite32A( Sttx34aM, GYRA34_MID ); // 0x188F
RamWrite32A( Sttx34aH, GYRA34_HGH ); // 0x189F
RamWrite32A( Sttx34bM, GYRB34_MID ); // 0x18AF
RamWrite32A( Sttx34bH, GYRB34_HGH ); // 0x18BF
RamWrite32A( SttyaL, 0x00000000 ); // 0x19AE
RamWrite32A( SttybL, 0x00000000 ); // 0x19BE
RamWrite32A( Stty12aM, GYRA12_MID ); // 0x194F
RamWrite32A( Stty12aH, GYRA12_HGH ); // 0x195F
RamWrite32A( Stty12bM, GYRB12_MID ); // 0x196F
RamWrite32A( Stty12bH, GYRB12_HGH ); // 0x197F
RamWrite32A( Stty34aM, GYRA34_MID ); // 0x198F
RamWrite32A( Stty34aH, GYRA34_HGH ); // 0x199F
RamWrite32A( Stty34bM, GYRB34_MID ); // 0x19AF
RamWrite32A( Stty34bH, GYRB34_HGH ); // 0x19BF
// Pan level
RegWriteA( GPANLEVABS, 0x00 ); // 0x0164
// Average
RegWriteA( GPANSTT1DWNSMP0, 0x00 ); // 0x0134
RegWriteA( GPANSTT1DWNSMP1, 0x00 ); // 0x0135
RegWriteA( GPANSTT2DWNSMP0, 0x90 ); // 0x0136
RegWriteA( GPANSTT2DWNSMP1, 0x01 ); // 0x0137
RegWriteA( GPANSTT3DWNSMP0, 0x64 ); // 0x0138
RegWriteA( GPANSTT3DWNSMP1, 0x00 ); // 0x0139
RegWriteA( GPANSTT4DWNSMP0, 0x00 ); // 0x013A
RegWriteA( GPANSTT4DWNSMP1, 0x00 ); // 0x013B
RegWriteA( GMEANAUTO, 0x01 ); // 0x015E Auto
// Force State
RegWriteA( GPANSTTFRCE, 0x00 ); // 0x010A not use force state
// Phase Transition Setting
// State 2 -> 1
RegWriteA( GPANSTT21JUG0, 0x00 ); // 0x0140
RegWriteA( GPANSTT21JUG1, 0x00 ); // 0x0141
// State 3 -> 1
RegWriteA( GPANSTT31JUG0, 0x00 ); // 0x0142
RegWriteA( GPANSTT31JUG1, 0x00 ); // 0x0143
// State 4 -> 1
RegWriteA( GPANSTT41JUG0, 0x01 ); // 0x0144
RegWriteA( GPANSTT41JUG1, 0x00 ); // 0x0145
// State 1 -> 2
RegWriteA( GPANSTT12JUG0, 0x00 ); // 0x0146
RegWriteA( GPANSTT12JUG1, 0x07 ); // 0x0147
// State 1 -> 3
RegWriteA( GPANSTT13JUG0, 0x00 ); // 0x0148
RegWriteA( GPANSTT13JUG1, 0x00 ); // 0x0149
// State 2 -> 3
RegWriteA( GPANSTT23JUG0, 0x11 ); // 0x014A
RegWriteA( GPANSTT23JUG1, 0x00 ); // 0x014B
// State 4 -> 3
RegWriteA( GPANSTT43JUG0, 0x00 ); // 0x014C
RegWriteA( GPANSTT43JUG1, 0x00 ); // 0x014D
// State 3 -> 4
RegWriteA( GPANSTT34JUG0, 0x01 ); // 0x014E
RegWriteA( GPANSTT34JUG1, 0x00 ); // 0x014F
// State 2 -> 4
RegWriteA( GPANSTT24JUG0, 0x00 ); // 0x0150
RegWriteA( GPANSTT24JUG1, 0x00 ); // 0x0151
// State 4 -> 2
RegWriteA( GPANSTT42JUG0, 0x44 ); // 0x0152
RegWriteA( GPANSTT42JUG1, 0x04 ); // 0x0153
// State Timer
RegWriteA( GPANSTT1LEVTMR, 0x00 ); // 0x0160
RegWriteA( GPANSTT2LEVTMR, 0x00 ); // 0x0161
RegWriteA( GPANSTT3LEVTMR, 0x00 ); // 0x0162
RegWriteA( GPANSTT4LEVTMR, 0x03 ); // 0x0163
// Control filter
RegWriteA( GPANTRSON0, 0x01 ); // 0x0132
RegWriteA( GPANTRSON1, 0x1C ); // 0x0133
// State Setting
IniPtMovMod( OFF ) ; // Pan/Tilt setting (Still)
// Hold
RegWriteA( GPANSTTSETILHLD, 0x00 ); // 0x0168
// HPS
RegWriteA( GPANSTTSETHPS, 0xF0 ); // 0x015C
RegWriteA( GHPSMOD, 0x00 ); // 0x016F
RegWriteA( GPANHPSTMR0, 0x5C ); // 0x016A
RegWriteA( GPANHPSTMR1, 0x00 ); // 0x016B
// State2,4 Step Time Setting
RegWriteA( GPANSTT2TMR0, 0x01 ); // 0x013C
RegWriteA( GPANSTT2TMR1, 0x00 ); // 0x013D
RegWriteA( GPANSTT4TMR0, 0x02 ); // 0x013E
RegWriteA( GPANSTT4TMR1, 0x00 ); // 0x013F
RegWriteA( GPANSTTXXXTH, 0x00 ); // 0x015D
#ifdef GAIN_CONT
RamWrite32A( gxlevmid, TRI_LEVEL ); // 0x182D Low Th
RamWrite32A( gxlevhgh, TRI_HIGH ); // 0x182E Hgh Th
RamWrite32A( gylevmid, TRI_LEVEL ); // 0x192D Low Th
RamWrite32A( gylevhgh, TRI_HIGH ); // 0x192E Hgh Th
RamWrite32A( gxadjmin, XMINGAIN ); // 0x18BA Low gain
RamWrite32A( gxadjmax, XMAXGAIN ); // 0x18BB Hgh gain
RamWrite32A( gxadjdn, XSTEPDN ); // 0x18BC -step
RamWrite32A( gxadjup, XSTEPUP ); // 0x18BD +step
RamWrite32A( gyadjmin, YMINGAIN ); // 0x19BA Low gain
RamWrite32A( gyadjmax, YMAXGAIN ); // 0x19BB Hgh gain
RamWrite32A( gyadjdn, YSTEPDN ); // 0x19BC -step
RamWrite32A( gyadjup, YSTEPUP ); // 0x19BD +step
RegWriteA( GLEVGXADD, (unsigned char)XMONADR ); // 0x0120 Input signal
RegWriteA( GLEVGYADD, (unsigned char)YMONADR ); // 0x0124 Input signal
RegWriteA( GLEVTMR, TIMEBSE ); // 0x0124 Base Time
RegWriteA( GLEVTMRLOWGX, TIMELOW ); // 0x0121 X Low Time
RegWriteA( GLEVTMRMIDGX, TIMEMID ); // 0x0122 X Mid Time
RegWriteA( GLEVTMRHGHGX, TIMEHGH ); // 0x0123 X Hgh Time
RegWriteA( GLEVTMRLOWGY, TIMELOW ); // 0x0125 Y Low Time
RegWriteA( GLEVTMRMIDGY, TIMEMID ); // 0x0126 Y Mid Time
RegWriteA( GLEVTMRHGHGY, TIMEHGH ); // 0x0127 Y Hgh Time
RegWriteA( GLEVFILMOD, 0x00 ); // 0x0129 select output signal
RegWriteA( GADJGANADD, (unsigned char)GANADR ); // 0x012A control address
RegWriteA( GADJGANGO, 0x00 ); // 0x0108 manual off
/* exe function */
AutoGainControlSw( OFF ) ; /* Auto Gain Control Mode OFF */
#endif
/*Gyro Filter On*/
RegWriteA( GEQON , 0x01 ); // 0x0100 [ - | - | - | - ][ - | - | - | CmEqOn ]
}
void HtcActOisBinder_open_init(void)
{
uint8_t ois_data_8;
uint16_t ois_data_16;
unsigned long ois_data_32;
if (binder_i2c_client == NULL)
return;
pr_info("[OIS] %s start\n", __func__);
pr_info("[OIS] %s FW_Version=0x%x\n", __func__, RdFwVr());
#if 0
RegReadA_lc898111(0x027F, &ois_data_8);
pr_info("[OIS] 0x027F read : 0x%x\n", ois_data_8);
#endif
IniSet();
if (g_otp_size > 0)
{
pr_info("[OIS] %s g_otp_size=%d\n", __func__, g_otp_size);
ois_data_16 = (g_otp_data[0] << 8) + g_otp_data[1];
RamWriteA_lc898111(0x1114, ois_data_16);
ois_data_16 = (g_otp_data[2] << 8) + g_otp_data[3];
RamWriteA_lc898111(0x1116, ois_data_16);
ois_data_16 = (g_otp_data[4] << 8) + g_otp_data[5];
RamWriteA_lc898111(0x1115, ois_data_16);
ois_data_16 = (g_otp_data[6] << 8) + g_otp_data[7];
RamWriteA_lc898111(0x1117, ois_data_16);
ois_data_16 = (g_otp_data[8] << 8) + g_otp_data[9];
RamWriteA_lc898111(0x1102, ois_data_16);
ois_data_16 = (g_otp_data[10] << 8) + g_otp_data[11];
RamWriteA_lc898111(0x1105, ois_data_16);
ois_data_16 = (g_otp_data[12] << 8) + g_otp_data[13];
RamWriteA_lc898111(0x132A, ois_data_16);
ois_data_16 = (g_otp_data[14] << 8) + g_otp_data[15];
RamWriteA_lc898111(0x136A, ois_data_16);
ois_data_16 = (g_otp_data[16] << 8) + g_otp_data[17];
RamWriteA_lc898111(0x1127, ois_data_16);
ois_data_16 = (g_otp_data[18] << 8) + g_otp_data[19];
RamWriteA_lc898111(0x1167, ois_data_16);
ois_data_8 = g_otp_data[20];
RegWriteA_lc898111(0x03A0, ois_data_8);
ois_data_8 = g_otp_data[21];
RegWriteA_lc898111(0x03A1, ois_data_8);
ois_data_8 = g_otp_data[22];
RegWriteA_lc898111(0x03A2, ois_data_8);
ois_data_8 = g_otp_data[23];
RegWriteA_lc898111(0x03A3, ois_data_8);
pr_info("[OIS] Gyro Gain X0 : 0x%x\n", g_otp_data[24]);
g_otp_data[24] = g_otp_data[24] | 0x80;
pr_info("[OIS] Corrected Gyro Gain X0 : 0x%x\n", g_otp_data[24]);
ois_data_32 = (g_otp_data[24] << 24) + (g_otp_data[25] << 16) + (g_otp_data[26] << 8) + g_otp_data[27];
RamWrite32A(0x1828, ois_data_32);
ois_data_32 = (g_otp_data[28] << 24) + (g_otp_data[29] << 16) + (g_otp_data[30] << 8) + g_otp_data[31];
RamWrite32A(0x1928, ois_data_32);
ois_data_8 = g_otp_data[32];
RegWriteA_lc898111(0x0264, ois_data_8);
}
#if 0
RamWrite32A( 0x1808, 0x3F99999A ) ;
RamWrite32A( 0x1809, 0x3F99999A ) ;
RamWrite32A( 0x1908, 0x3F99999A ) ;
RamWrite32A( 0x1909, 0x3F99999A ) ;
#endif
RtnCen(0);
SetPanTiltMode(ON);
pr_info("[OIS] %s g_ois_mode=%d\n", __func__, g_ois_mode);
if (g_ois_mode != 0) {
ClrGyr(0x06, CLR_GYR_DLY_RAM);
OisEna();
SetGcf(5);
}
#if 0
RegReadA_lc898111(0x0084, &ois_data_8);
pr_info("[OIS] 0x0084 read : 0x%x\n", ois_data_8);
RamReadA_lc898111(0x1308, &ois_data_16);
pr_info("[OIS] 0x1308 read : 0x%x\n", ois_data_16);
RegReadA_lc898111(0x0084, &ois_data_8);
pr_info("[OIS] 0x0084 read : 0x%x\n", ois_data_8);
RamReadA_lc898111(0x1348, &ois_data_16);
pr_info("[OIS] 0x1348 read : 0x%x\n", ois_data_16);
#endif
pr_info("[OIS] %s end\n", __func__);
}