Exemplo n.º 1
0
/* ===================================================================*/
LDD_TError SPI_SD_SelectConfiguration(LDD_TDeviceData *DeviceDataPtr, uint8_t ChipSelect, uint8_t AttributeSet)
{
  /* Clock configuration test - this test can be disabled by setting the "Ignore clock configuration test"
     property to the "yes" value in the "Configuration inspector" */
  if (!((SPI_SD_TDeviceDataPtr)DeviceDataPtr)->EnMode) { /* Is the device disabled in the actual speed CPU mode? */
    return ERR_SPEED;                  /* If yes then error */
  }
  (void)ChipSelect;                    /* Parameter is not used, suppress unused argument warning */
  if (AttributeSet >= SPI_SD_CONFIGURATION_COUNT) { /* Is Attribute set index out of range? */
    return ERR_PARAM_ATTRIBUTE_SET;    /* Yes, return ERR_PARAM */
  }
  if ((((SPI_SD_TDeviceDataPtr)DeviceDataPtr)->InpDataNumReq != 0x00U) || (((SPI_SD_TDeviceDataPtr)DeviceDataPtr)->OutDataNumReq != 0x00U)) { /* Is the previous receive operation pending? */
    return ERR_BUSY;                   /* If yes then error */
  }
  ((SPI_SD_TDeviceDataPtr)DeviceDataPtr)->CurrentAttributeSet = AttributeSet; /* Set current attribute set */
  SPI_PDD_EnableHaltMode(SPI1_BASE_PTR,PDD_ENABLE); /* Enter to STOPPED mode */
  while (SPI_PDD_GetTxRxActiveFlag(SPI1_BASE_PTR)) {} /* Wait until the current transmission finished */
  switch (Cpu_GetClockConfiguration()) {
    case CPU_CLOCK_CONFIG_0:
      SPI_PDD_WriteMasterClockTransferAttributeReg(SPI1_BASE_PTR,0U,ConfigurationSet0[AttributeSet]); /* Set required configuration */
      break;
    default:
      break;
  }
  ((SPI_SD_TDeviceDataPtr)DeviceDataPtr)->TxCommand = TxCommandList[AttributeSet]; /* Prepare command for transmision */
  SPI_PDD_EnableHaltMode(SPI1_BASE_PTR,PDD_DISABLE); /* Leave the STOPPED mode */
  return ERR_OK;                       /* OK */
}
Exemplo n.º 2
0
/*
** ===================================================================
**     Method      :  _bsp_get_clock_configuration
**
**     Description :
**         Returs the active clock configuration identifier.
**     Parameters  : None
**     Returns     :
**         ---             - Active clock configuration identifier
** ===================================================================
*/
BSP_CLOCK_CONFIGURATION _bsp_get_clock_configuration
(
    void
)
{
    return (BSP_CLOCK_CONFIGURATION)Cpu_GetClockConfiguration();
}
Exemplo n.º 3
0
/* ===================================================================*/
LDD_TDeviceData* UART_Init(LDD_TUserData *UserDataPtr)
{
    /* Allocate device structure */
    UART_TDeviceDataPtr DeviceDataPrv;
    /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
    DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;

    /* Clear the receive counters and pointer */
    DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
    DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
    DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
    /* Clear the transmit counters and pointer */
    DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
    DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
    DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
    DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
    /* Allocate interrupt vectors */
    /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
    INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
    /* SIM_SCGC4: UART0=1 */
    SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
    /* PORTA_PCR1: ISF=0,MUX=2 */
    PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)(
                                 PORT_PCR_ISF_MASK |
                                 PORT_PCR_MUX(0x05)
                             )) | (uint32_t)(
                                PORT_PCR_MUX(0x02)
                            ));
    /* PORTA_PCR2: ISF=0,MUX=2 */
    PORTA_PCR2 = (uint32_t)((PORTA_PCR2 & (uint32_t)~(uint32_t)(
                                 PORT_PCR_ISF_MASK |
                                 PORT_PCR_MUX(0x05)
                             )) | (uint32_t)(
                                PORT_PCR_MUX(0x02)
                            ));
    /* NVIC_IPR3: PRI_12=0x80 */
    NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
                                NVIC_IP_PRI_12(0x7F)
                            )) | (uint32_t)(
                               NVIC_IP_PRI_12(0x80)
                           ));
    /* NVIC_ISER: SETENA|=0x1000 */
    NVIC_ISER |= NVIC_ISER_SETENA(0x1000);
    UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
    UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
    DeviceDataPrv->SerFlag = 0x00U;      /* Reset flags */
    /* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
    UART0_C1 = 0x00U;                    /*  Set the C1 register */
    /* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
    UART0_C3 = 0x00U;                    /*  Set the C3 register */
    /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */
    UART0_C4 = UART0_C4_OSR(0x00);       /*  Set the C4 register */
    /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
    UART0_S2 = 0x00U;                    /*  Set the S2 register */
    UART_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Initial speed CPU mode is high */
    /* Registration of the device structure */
    PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_ID,DeviceDataPrv);
    return ((LDD_TDeviceData *)DeviceDataPrv);
}
/* ===================================================================*/
LDD_TDeviceData* TimerIntLdd3_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  TimerIntLdd3_TDeviceData *DeviceDataPrv;
  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  DeviceDataPrv->EnUser = TRUE;        /* Set the flag "device enabled" */
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TimerIntLdd3_ID,DeviceDataPrv);
  DeviceDataPrv->LinkedDeviceDataPtr = TU3_Init((LDD_TUserData *)NULL);
  if (DeviceDataPrv->LinkedDeviceDataPtr == NULL) { /* Is initialization of TimerUnit unsuccessful? */
    /* Unregistration of the device structure */
    PE_LDD_UnregisterDeviceStructure(PE_LDD_COMPONENT_TimerIntLdd3_ID);
    /* Deallocation of the device structure */
    /* {Default RTOS Adapter} Driver memory deallocation: Dynamic allocation is simulated, no deallocation code is generated */
    return NULL;                       /* If so, then the TimerInt initialization is also unsuccessful */
  }
  TimerIntLdd3_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according clock configuration */
  return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */
}
Exemplo n.º 5
0
/* ===================================================================*/
LDD_TDeviceData* SPI_SD_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate LDD device structure */
  SPI_SD_TDeviceDataPtr DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
  /* Interrupt vector(s) allocation */
  /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_SPI1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
  DeviceDataPrv->TxCommand = 0x80000000U; /* Initialization of current Tx command */
  DeviceDataPrv->ErrFlag = 0x00U;      /* Clear error flags */
  /* Clear the receive counters and pointer */
  DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
  DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
  DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
  /* Clear the transmit counters and pointer */
  DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
  DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
  DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
  DeviceDataPrv->CurrentAttributeSet = 0U; /* Init current attribute set */
  DeviceDataPrv->SerFlag = 0x00U;      /* Reset flags */
  /* SIM_SCGC6: SPI1=1 */
  SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
  /* Interrupt vector(s) priority setting */
  /* NVICIP27: PRI27=0x70 */
  NVICIP27 = NVIC_IP_PRI27(0x70);
  /* NVICISER0: SETENA|=0x08000000 */
  NVICISER0 |= NVIC_ISER_SETENA(0x08000000);
  /* SIM_SCGC5: PORTD=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
  /* PORTD_PCR7: ISF=0,MUX=7 */
  PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
  /* PORTD_PCR6: ISF=0,MUX=7 */
  PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
  /* PORTD_PCR5: ISF=0,MUX=7 */
  PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
  /* SPI1_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
  SPI1_MCR = SPI_MCR_DCONF(0x00) |
             SPI_MCR_ROOE_MASK |
             SPI_MCR_PCSIS(0x00) |
             SPI_MCR_SMPL_PT(0x00) |
             SPI_MCR_HALT_MASK;        /* Set Configuration register */
  /* SPI1_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
  SPI1_MCR = SPI_MCR_MSTR_MASK |
             SPI_MCR_DCONF(0x00) |
             SPI_MCR_ROOE_MASK |
             SPI_MCR_PCSIS(0x00) |
             SPI_MCR_DIS_TXF_MASK |
             SPI_MCR_DIS_RXF_MASK |
             SPI_MCR_CLR_TXF_MASK |
             SPI_MCR_CLR_RXF_MASK |
             SPI_MCR_SMPL_PT(0x00) |
             SPI_MCR_HALT_MASK;        /* Set Configuration register */
  /* SPI1_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=0,CSSCK=0,ASC=0,DT=0,BR=0 */
  SPI1_CTAR0 = SPI_CTAR_DBR_MASK |
               SPI_CTAR_FMSZ(0x07) |
               SPI_CTAR_PCSSCK(0x00) |
               SPI_CTAR_PASC(0x00) |
               SPI_CTAR_PDT(0x00) |
               SPI_CTAR_PBR(0x00) |
               SPI_CTAR_CSSCK(0x00) |
               SPI_CTAR_ASC(0x00) |
               SPI_CTAR_DT(0x00) |
               SPI_CTAR_BR(0x00);      /* Set Clock and Transfer Attributes register */
  /* SPI1_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */
  SPI1_SR = SPI_SR_TCF_MASK |
            SPI_SR_EOQF_MASK |
            SPI_SR_TFUF_MASK |
            SPI_SR_TFFF_MASK |
            SPI_SR_RFOF_MASK |
            SPI_SR_RFDF_MASK |
            SPI_SR_TXCTR(0x00) |
            SPI_SR_TXNXTPTR(0x00) |
            SPI_SR_RXCTR(0x00) |
            SPI_SR_POPNXTPTR(0x00) |
            0x00200000U;               /* Clear flags */
  /* SPI1_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SPI1_RSER = SPI_RSER_RFDF_RE_MASK;   /* Set DMA Interrupt Request Select and Enable register */
  SPI_SD_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according speed CPU mode */
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SPI_SD_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
Exemplo n.º 6
0
/* ===================================================================*/
LDD_TDeviceData* UART_SDA_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  UART_SDA_TDeviceDataPtr DeviceDataPrv;
  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;

  /* Clear the receive counters and pointer */
  DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
  DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
  DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
  /* Clear the transmit counters and pointer */
  DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
  DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
  DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  /* Allocate interrupt vectors */
  /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_UART0_RX_TX__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
  /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_UART0_ERR__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
  /* SIM_SCGC4: UART0=1 */
  SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
  /* SIM_SCGC5: PORTB=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;
  /* PORTB_PCR16: ISF=0,MUX=3 */
  PORTB_PCR16 = (uint32_t)((PORTB_PCR16 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x04)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x03)
                ));
  /* PORTB_PCR17: ISF=0,MUX=3 */
  PORTB_PCR17 = (uint32_t)((PORTB_PCR17 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x04)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x03)
                ));
  /* NVICIP31: PRI31=0x70 */
  NVICIP31 = NVIC_IP_PRI31(0x70);
  /* NVICISER0: SETENA|=0x80000000 */
  NVICISER0 |= NVIC_ISER_SETENA(0x80000000);
  /* NVICIP32: PRI32=0x70 */
  NVICIP32 = NVIC_IP_PRI32(0x70);
  /* NVICISER1: SETENA|=1 */
  NVICISER1 |= NVIC_ISER_SETENA(0x01);
  UART_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
  UART_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
  DeviceDataPrv->SerFlag = 0x00U;      /* Reset flags */
  /* UART0_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
  UART0_C1 = 0x00U;                    /*  Set the C1 register */
  /* UART0_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
  UART0_C3 = 0x00U;                    /*  Set the C3 register */
  /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,BRFA=0 */
  UART0_C4 = UART_C4_BRFA(0x00);       /*  Set the C4 register */
  /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
  UART0_S2 = 0x00U;                    /*  Set the S2 register */
  /* UART0_MODEM: ??=0,??=0,??=0,??=0,RXRTSE=0,TXRTSPOL=0,TXRTSE=0,TXCTSE=0 */
  UART0_MODEM = 0x00U;                 /*  Set the MODEM register */
  UART_SDA_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Initial speed CPU mode is high */
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_UART_SDA_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}