Exemplo n.º 1
0
static void ppc440spe_setup_utl(u32 port) {

	volatile void *utl_base = NULL;

	/*
	 * Map UTL registers
	 */
	switch (port) {
	case 0:
		mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
		mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
		mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
		mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
		break;

	case 1:
		mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
		mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
		mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
		mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
		break;

	case 2:
		mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
		mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
		mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
		mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
		break;
	}
	utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);

	/*
	 * Set buffer allocations and then assert VRB and TXE.
	 */
	out_be32(utl_base + PEUTL_OUTTR,   0x08000000);
	out_be32(utl_base + PEUTL_INTR,    0x02000000);
	out_be32(utl_base + PEUTL_OPDBSZ,  0x10000000);
	out_be32(utl_base + PEUTL_PBBSZ,   0x53000000);
	out_be32(utl_base + PEUTL_IPHBSZ,  0x08000000);
	out_be32(utl_base + PEUTL_IPDBSZ,  0x10000000);
	out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
	out_be32(utl_base + PEUTL_PCTL,    0x80800066);
}
Exemplo n.º 2
0
int ppc440spe_init_pcie_rootport(int port)
{
    static int core_init;
    void __iomem *utl_base;
    u32 val = 0;
    int i;

    if (!core_init) {
        ++core_init;
        i = ppc440spe_init_pcie();
        if (i)
            return i;
    }

    /*
     * Initialize various parts of the PCI Express core for our port:
     *
     * - Set as a root port and enable max width
     *   (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
     * - Set up UTL configuration.
     * - Increase SERDES drive strength to levels suggested by AMCC.
     * - De-assert RSTPYN, RSTDL and RSTGU.
     */
    switch (port) {
    case 0:
        SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);

        SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
        SDR_WRITE(PESDR0_UTLSET2, 0x11000000);

        SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
        SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
        SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
        SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
        SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
        SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
        SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
        SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);

        SDR_WRITE(PESDR0_RCSSET,
              (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
        break;

    case 1:
        SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);

        SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
        SDR_WRITE(PESDR1_UTLSET2, 0x11000000);

        SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
        SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
        SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
        SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);

        SDR_WRITE(PESDR1_RCSSET,
              (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
        break;

    case 2:
        SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);

        SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
        SDR_WRITE(PESDR2_UTLSET2, 0x11000000);

        SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
        SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
        SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
        SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);

        SDR_WRITE(PESDR2_RCSSET,
              (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
        break;
    }

    mdelay(1000);

    switch (port) {
    case 0: val = SDR_READ(PESDR0_RCSSTS); break;
    case 1: val = SDR_READ(PESDR1_RCSSTS); break;
    case 2: val = SDR_READ(PESDR2_RCSSTS); break;
    }

    if (!(val & (1 << 20)))
        printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
    else
        printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);

    switch (port) {
    case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
    case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
    case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
    }

    /*
     * Map UTL registers at 0xc_1000_0n00
     */
    switch (port) {
    case 0:
        mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
        mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
        mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
        mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
        break;

    case 1:
        mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
        mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
        mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
        mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
        break;

    case 2:
        mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
        mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000);
        mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
        mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
    }

    utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100);

    /*
     * Set buffer allocations and then assert VRB and TXE.
     */
    out_be32(utl_base + PEUTL_OUTTR,   0x08000000);
    out_be32(utl_base + PEUTL_INTR,    0x02000000);
    out_be32(utl_base + PEUTL_OPDBSZ,  0x10000000);
    out_be32(utl_base + PEUTL_PBBSZ,   0x53000000);
    out_be32(utl_base + PEUTL_IPHBSZ,  0x08000000);
    out_be32(utl_base + PEUTL_IPDBSZ,  0x10000000);
    out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
    out_be32(utl_base + PEUTL_PCTL,    0x80800066);

    iounmap(utl_base);

    /*
     * We map PCI Express configuration access into the 512MB regions
     *     PCIE0: 0xc_4000_0000
     *     PCIE1: 0xc_8000_0000
     *     PCIE2: 0xc_c000_0000
     */
    switch (port) {
    case 0:
        mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
        mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
        mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
        break;

    case 1:
        mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
        mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
        mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
        break;

    case 2:
        mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
        mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
        mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
        break;
    }

    /*
     * Check for VC0 active and assert RDY.
     */
    switch (port) {
    case 0:
        if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
            printk(KERN_WARNING "PCIE0: VC0 not active\n");
        SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
        break;
    case 1:
        if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
            printk(KERN_WARNING "PCIE0: VC0 not active\n");
        SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
        break;
    case 2:
        if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
            printk(KERN_WARNING "PCIE0: VC0 not active\n");
        SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
        break;
    }

#if 0
    /* Dump all config regs */
    for (i = 0x300; i <= 0x320; ++i)
        printk("[%04x] 0x%08x\n", i, SDR_READ(i));
    for (i = 0x340; i <= 0x353; ++i)
        printk("[%04x] 0x%08x\n", i, SDR_READ(i));
    for (i = 0x370; i <= 0x383; ++i)
        printk("[%04x] 0x%08x\n", i, SDR_READ(i));
    for (i = 0x3a0; i <= 0x3a2; ++i)
        printk("[%04x] 0x%08x\n", i, SDR_READ(i));
    for (i = 0x3c0; i <= 0x3c3; ++i)
        printk("[%04x] 0x%08x\n", i, SDR_READ(i));
#endif

    mdelay(100);

    return 0;
}