static void
ppc405_uic_end(unsigned int irq)
{
int bit, word;
unsigned int tr_bits;
bit = irq & 0x1f;
word = irq >> 5;
#ifdef UIC_DEBUG
printk("ppc405_uic_end - irq %d word %d bit 0x%x\n", irq, word, bit);
#endif
switch (word) {
case 0:
tr_bits = mfdcr(DCRN_UIC_TR(UIC0));
break;
case 1:
tr_bits = mfdcr(DCRN_UIC_TR(UIC1));
break;
}
if ((tr_bits & (1 << (31 - bit))) == 0) {
/* level trigger */
switch (word) {
case 0:
mtdcr(DCRN_UIC_SR(UIC0), 1 << (31 - bit));
break;
case 1:
mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
break;
}
}
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
ppc_cached_irq_mask[word] |= 1 << (31 - bit);
switch (word) {
case 0:
mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
break;
case 1:
mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
break;
}
}
}
static void __init ppc4xx_pic_impl_init(void)
{
/* Configure Base UIC */
mtdcr(DCRN_UIC_CR(UICB), 0);
mtdcr(DCRN_UIC_TR(UICB), 0);
mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
}
static void
ppc405_uic_enable(unsigned int irq)
{
int bit, word;
irq_desc_t *desc = irq_desc + irq;
bit = irq & 0x1f;
word = irq >> 5;
#ifdef UIC_DEBUG
printk("ppc405_uic_enable - irq %d word %d bit 0x%x\n", irq, word, bit);
#endif
ppc_cached_irq_mask[word] |= 1 << (31 - bit);
switch (word) {
case 0:
mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[word]);
if ((mfdcr(DCRN_UIC_TR(UIC0)) & (1 << (31 - bit))) == 0)
desc->status |= IRQ_LEVEL;
else
/* lets hope this works since in linux/irq.h
* there is no define for EDGE and it's assumed
* once you set status to LEVEL you would not
* want to change it - Armin
*/
desc->status = desc->status & ~IRQ_LEVEL;
break;
case 1:
mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
if ((mfdcr(DCRN_UIC_TR(UIC1)) & (1 << (31 - bit))) == 0)
desc->status |= IRQ_LEVEL;
else
/* lets hope this works since in linux/irq.h
* there is no define for EDGE and it's assumed
* once you set status to LEVEL you would not
* want to change it - Armin
*/
desc->status = desc->status & ~IRQ_LEVEL;
break;
}
}
static void __init ppc4xx_pic_impl_init(void)
{
#if defined(CONFIG_440GX)
/* Disable 440GP compatibility mode if it was enabled in firmware */
SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~DCRN_SDR_MFR_PCM);
#endif
/* Configure Base UIC */
mtdcr(DCRN_UIC_CR(UICB), 0);
mtdcr(DCRN_UIC_TR(UICB), 0);
mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
}
void __init
ppc4xx_extpic_init(void)
{
/* set polarity
* 1 = default/pos/rising , 0= neg/falling internal
* 1 = neg/falling , 0= pos/rising external
* Sense
* 0 = default level internal
* 0 = level, 1 = edge external
*/
unsigned int sense, irq;
int bit, word;
unsigned long ppc_cached_sense_mask[NR_MASK_WORDS];
unsigned long ppc_cached_pol_mask[NR_MASK_WORDS];
ppc_cached_sense_mask[0] = 0;
ppc_cached_sense_mask[1] = 0;
ppc_cached_pol_mask[0] = 0;
ppc_cached_pol_mask[1] = 0;
for (irq = 0; irq < NR_IRQS; irq++) {
bit = irq & 0x1f;
word = irq >> 5;
sense =
(irq <
ibm4xxPIC_NumInitSenses) ? ibm4xxPIC_InitSenses[irq] : 3;
#ifdef PPC4xx_PIC_DEBUG
printk("PPC4xx_picext %d word:%x bit:%x sense:%x", irq, word,
bit, sense);
#endif
ppc_cached_sense_mask[word] |=
(sense & IRQ_SENSE_MASK) << (31 - bit);
ppc_cached_pol_mask[word] |=
((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit);
switch (word) {
case 0:
#ifdef PPC4xx_PIC_DEBUG
printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC0)));
printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC0)));
#endif
/* polarity setting */
mtdcr(DCRN_UIC_PR(UIC0), ppc_cached_pol_mask[word]);
/* Level setting */
mtdcr(DCRN_UIC_TR(UIC0), ppc_cached_sense_mask[word]);
break;
case 1:
#ifdef PPC4xx_PIC_DEBUG
printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC1)));
printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC1)));
#endif
/* polarity setting */
mtdcr(DCRN_UIC_PR(UIC1), ppc_cached_pol_mask[word]);
/* Level setting */
mtdcr(DCRN_UIC_TR(UIC1), ppc_cached_sense_mask[word]);
break;
}
}
}
