static void program_ddr0_43(unsigned long dimm_ranks[], unsigned char const iic0_dimm_addr[], unsigned long num_dimm_banks, unsigned long sdram_freq, unsigned long cols, unsigned long banks) { unsigned long dimm_num; unsigned long t_wr_ps = 0; unsigned long t_wr_clk; u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) | DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) | DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0); /*------------------------------------------------------------------ * Handle the timing. We need to find the worst case timing of all * the dimm modules installed. *-----------------------------------------------------------------*/ /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_ranks[dimm_num]) { unsigned long ps; ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36); t_wr_ps = max(t_wr_ps, ps); } } debug("t_wr_ps = %d\n", t_wr_ps); t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000; mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk)); }
/* * initdram -- 440EPx's DDR controller is a DENALI Core */ int initdram_by_rb(int rows, int banks) { ulong speed = get_bus_freq(0); mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030602); mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0102C812); mtsdram(DDR0_07, 0x000D0100); mtsdram(DDR0_08, 0x02430001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_11, 0x0027C800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x19000000); mtsdram(DDR0_18, 0x19191919); mtsdram(DDR0_19, 0x19191919); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); mtsdram(DDR0_22, 0x00267F0B); mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01010002); if (speed > 133333334) mtsdram(DDR0_26, 0x5B26050C); else mtsdram(DDR0_26, 0x5B260408); mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | 0x00000006); mtsdram(DDR0_43, DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) | 0x030A0200); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); #ifdef CONFIG_DDR_DATA_EYE /* * Perform data eye search if requested. */ denali_core_search_data_eye(); #endif /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); return 0; }