static DDS_ReturnCode_t sequence_get(qeocore_data_t **value,
const DDS_DynamicData dyndata,
qeocore_member_id_t id,
DDS_DynamicType type)
{
DDS_ReturnCode_t ddsrc;
*value = data_alloc(type, 1);
if (NULL == *value) {
ddsrc = DDS_RETCODE_OUT_OF_RESOURCES;
}
else {
DDS_DynamicData seqdata;
ddsrc = DDS_DynamicData_get_complex_value(dyndata, &seqdata, id);
if (DDS_RETCODE_OK == ddsrc) {
/* actual data was returned */
DDS_DynamicDataFactory_delete_data((*value)->d.dynamic.single_data);
(*value)->d.dynamic.single_data = seqdata;
}
/* in case of DDS_RETCODE_NO_DATA we keep the preallocated data */
else if (DDS_RETCODE_NO_DATA != ddsrc) {
qeo_log_dds_rc("DDS_DynamicData_get_complex_value", ddsrc);
}
}
return ddsrc;
}
extern unsigned long dataAvailable;
/* Function prototypes */
unsigned char mp3_VS1053_attach(VOS_HANDLE spi_master_handle, unsigned char XRESET_GPIO_port, unsigned char XRESET_GPIO_pin, unsigned char DREQ_GPIO_port, unsigned char DREQ_GPIO_pin, unsigned char SDI_CS_identifier, unsigned char SCI_CS_identifier);
int mp3_VS1053_detach();
int mp3_VS1053_select_control(void);
int mp3_VS1053_deselect_control(void);
int mp3_VS1053_select_data(void);
int mp3_VS1053_deselect_data(void);
int mp3_VS1053_hard_reset(void);
int mp3_VS1053_soft_reset(void);
int mp3_VS1053_setup(void);
int mp3_VS1053_wait_for_dreq(void);
int mp3_VS1053_write_reg(unsigned char reg_address, unsigned short data);
int mp3_VS1053_read_reg(unsigned char reg_address, unsigned short *data);
unsigned short mp3_VS1053_read_ram(unsigned short ram_address);
unsigned char mp3_VS1053_write(unsigned char *buf, unsigned short num_to_write, unsigned short *num_written);
unsigned char mp3_VS1053_ioctl(void *cb);
void mp3_VS1053_init(unsigned char mp3VS1053DevNum, mp3_VS1053_context_t *mp3Context)
{
// Set up function pointers for our driver
mp3_VS1053_cb.flags = 0;
mp3_VS1053_cb.read = (PF_IO) NULL;
mp3_VS1053_cb.write = mp3_VS1053_write;
mp3_VS1053_cb.ioctl = mp3_VS1053_ioctl;
mp3_VS1053_cb.interrupt = (PF_INT) NULL;
static DDS_ReturnCode_t struct_get(qeocore_data_t **data,
const DDS_DynamicData dyndata,
qeocore_member_id_t id,
DDS_MemberDescriptor *mdesc)
{
DDS_ReturnCode_t ddsrc = DDS_RETCODE_OUT_OF_RESOURCES;
*data = calloc(1, sizeof(qeocore_data_t));
if (NULL != *data) {
(*data)->flags.is_single = 1;
ddsrc = DDS_DynamicData_get_complex_value(dyndata, &(*data)->d.dynamic.single_data, id);
if (DDS_RETCODE_NO_DATA == ddsrc) {
/* no nested structure there yet, create empty one */
(*data)->d.dynamic.single_data = DDS_DynamicDataFactory_create_data(mdesc->type);
qeo_log_dds_null("DDS_DynamicDataFactory_create_data", (*data)->d.dynamic.single_data);
if (NULL != (*data)->d.dynamic.single_data) {
ddsrc = DDS_RETCODE_OK;
}
}
else {
qeo_log_dds_rc("DDS_DynamicData_get_complex_value", ddsrc);
}
}
if (DDS_RETCODE_OK == ddsrc) {
/* take ownership of type for future use */
(*data)->d.dynamic.single_type = mdesc->type;
mdesc->type = NULL;
}
else {
if (NULL != *data) {
if (NULL != (*data)->d.dynamic.single_data) {
DDS_DynamicDataFactory_delete_data((*data)->d.dynamic.single_data);
}
free(*data);
}
}
return ddsrc;
}
#include "MP3_VS1053_defs.h" #include "devman.h" #define MP3_VS1053_BUFFER_SIZE 128 #define MASK_GPIO_EN (1 << 1) /* Port registers */ #define VII_GPIO_SYS_CNTRL_1 0x180 /* GPIO Control Register */ #define VII_GPIO_CNTRL_PORTA_1 0x181 #define VII_GPIO_CNTRL_PORTB_1 0x182 #define VII_GPIO_CNTRL_PORTC_1 0x183 #define VII_GPIO_CNTRL_PORTD_1 0x184 #define VII_GPIO_CNTRL_PORTE_1 0x185 #define VII_GPIO_DATA_TX_PA_1 0x186 #define VII_GPIO_DATA_TX_PB_1 0x187 #define VII_GPIO_DATA_TX_PC_1 0x188 #define VII_GPIO_DATA_TX_PD_1 0x189 #define VII_GPIO_DATA_TX_PE_1 0x18a #define VII_GPIO_DATA_RX_PA_1 0x18b #define VII_GPIO_DATA_RX_PB_1 0x18c #define VII_GPIO_DATA_RX_PC_1 0x18d #define VII_GPIO_DATA_RX_PD_1 0x18e #define VII_GPIO_DATA_RX_PE_1 0x18f #define VII_GPIO_INT_REG_EN_1 0x19a /* GPIO Interrupt Register */ port vII_gpio_sys_cntrl_1 @ VII_GPIO_SYS_CNTRL_1; port vII_gpio_cntrl_porta_1 @ VII_GPIO_CNTRL_PORTA_1; port vII_gpio_cntrl_portb_1 @ VII_GPIO_CNTRL_PORTB_1; port vII_gpio_cntrl_portc_1 @ VII_GPIO_CNTRL_PORTC_1; port vII_gpio_cntrl_portd_1 @ VII_GPIO_CNTRL_PORTD_1; port vII_gpio_cntrl_porte_1 @ VII_GPIO_CNTRL_PORTE_1; port vII_gpio_data_tx_pa_1 @ VII_GPIO_DATA_TX_PA_1; port vII_gpio_data_tx_pb_1 @ VII_GPIO_DATA_TX_PB_1; port vII_gpio_data_tx_pc_1 @ VII_GPIO_DATA_TX_PC_1; port vII_gpio_data_tx_pd_1 @ VII_GPIO_DATA_TX_PD_1; port vII_gpio_data_tx_pe_1 @ VII_GPIO_DATA_TX_PE_1;
