void exynos_dp_init_aux(void)
{
u32 reg;
/* Clear interrupts related to AUX channel */
reg = RPLY_RECEIV | AUX_ERR;
lwrite32(reg, &dp_regs->int_sta);
exynos_dp_reset_aux();
/* Disable AUX transaction H/W retry */
reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
lwrite32(reg, &dp_regs->aux_hw_retry_ctl);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
reg = DEFER_CTRL_EN | DEFER_COUNT(1);
lwrite32(reg, &dp_regs->aux_ch_defer_ctl);
/* Enable AUX channel module */
reg = lread32(&dp_regs->func_en2);
reg &= ~AUX_FUNC_EN_N;
lwrite32(reg, &dp_regs->func_en2);
return;
}
static void rk_edp_init_aux(struct rk_edp *edp)
{
/* Clear inerrupts related to AUX channel */
write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N);
/* Disable AUX channel module */
setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1));
/* Enable AUX channel module */
clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N);
}
