void Init_PWM (eventptr cbk)
{
DEFINE_EVENT(PWM_OVERFLOW, cbk);
/* Reglage du timer 4 -> PWM pour bras haut*/
RCC->APB1ENR |= RCC_TIM4EN; /* Mise en route de l'horloge du timer 4 */
TIM4->CNT = 0; /* On cale le timer juste apres (pas de risque de se prendre une IT avant la fin de l'init) */
TIM4->PSC = 0;
TIM4->ARR = 0x3FF; /*_PERIODE_PWM_TIM4_; Periode de PWM -> 40Khz */
TIM4->SMCR |= TIM_SMS_IS_DISABLED; /* Desactivation du SMS */
TIM4->CCER = 0x0100;
TIM4->CCMR2 = TIM_OC3M_VAL(TIM_OCxM_PWM_1) + TIM_CC3S_IS_OUTPUT + TIM_OC3PE ;
TIM4->CCR3 = 0;
TIM4->DIER |= TIM_UIE; /* Active les IT overflow */
/* Regle les bras du hacheur en sortie */
/* Reglage du port B */
RCC->APB2ENR |= RCC_IOPBEN; /* Mise en route de l'horloge du port A */
GPIOB->ODR |= GPIO_PIN_8;
GPIOB->CRH &= ~((3<<GPIO_MODE_8_SHIFT) + (3<<GPIO_CNF_8_SHIFT));
GPIOB->CRH |= (GPIO_MODE_OUTPUT_50_MHZ<<GPIO_MODE_8_SHIFT) + (GPIO_CNF_ALTERNATE_PUSH_PULL<<GPIO_CNF_8_SHIFT);
TIM4->CR1 |= TIM_CEN;
}
/*
* ActiveITOverflow
*
* Enregistre un callback sur l'IT timer 2
* Active automatiquement les IT sur overflow
*/
void ActiveITOverflow(eventptr cbk)
{
DEFINE_EVENT(PWM_OVERFLOW, cbk);
/* Activer l'IT Timer2 overflow */
TIM2->DIER |= TIM_UIE;
}
void
Init_gst_event (VALUE mGst)
{
RGConvertTable table;
memset(&table, 0, sizeof(RGConvertTable));
table.type = GST_TYPE_EVENT;
table.get_superclass = get_superclass;
table.instance2robj = instance2robj;
RG_DEF_CONVERSION(&table);
rb_cGstEvent = G_DEF_CLASS(GST_TYPE_EVENT, "Event", mGst);
rbg_define_method(rb_cGstEvent, "get_type", rbgst_event_get_type, 0);
G_DEF_CLASS(GST_TYPE_EVENT_TYPE, "EventType", mGst);
G_DEF_CONSTANTS(rb_cGstEvent, GST_TYPE_EVENT_TYPE, "GST_EVENT_");
#define DEFINE_EVENT(type, lctype, arguments) \
rb_cGstEvent ## type = \
rb_define_class_under(mGst, "Event" #type, rb_cGstEvent); \
rbg_define_method(rb_cGstEvent ## type, "initialize", \
lctype ## _initialize, arguments)
#define DEFINE_EVENT_PARSE(type, lctype, arguments) \
DEFINE_EVENT(type, lctype, arguments); \
rbg_define_method(rb_cGstEvent ## type, "parse", \
lctype ## _parse, 0)
DEFINE_EVENT(FlushStart, flush_start, 0);
DEFINE_EVENT(FlushStop, flush_stop, 0);
DEFINE_EVENT(EOS, eos, 0);
DEFINE_EVENT_PARSE(NewSegment, newsegment, 7);
DEFINE_EVENT_PARSE(Tag, tag, 1);
DEFINE_EVENT_PARSE(BufferSize, buffersize, 4);
DEFINE_EVENT_PARSE(QOS, qos, 3);
DEFINE_EVENT_PARSE(Seek, seek, 7);
DEFINE_EVENT(Navigation, navigation, 1);
DEFINE_EVENT_PARSE(Latency, latency, 1);
#undef DEFINE_EVENT_PARSE
#undef DEFINE_EVENT
}
/*
* Init_Hacheur
*
* Initialisation des bras haut et bas du hacheur
* Bras haut (PMOS) connecté au timer 2 (canaux 1,3 et 4)
* Bras bas (NMOS) connecté aux GPIO (pas de timer)
*/
void Init_Hacheur (void)
{
DeadTime = 8;
/* Init du callback sur une fonction vide */
DEFINE_EVENT(PWM_OVERFLOW, Default_Callback_Hacheur);
/* Reglage du timer 2 -> PWM pour bras haut*/
RCC->APB1ENR |= RCC_TIM2EN; /* Mise en route de l'horloge du timer 2 */
TIM2->CNT = 0; /* On cale le timer juste apres (pas de risque de se prendre une IT avant la fin de l'init) */
TIM2->PSC = 0;
TIM2->ARR = _PERIODE_PWM_TIM2_; /* Periode de PWM -> 20Khz */
TIM2->SMCR |= TIM_SMS_IS_DISABLED; /* Desactivation du SMS */
TIM2->CCER = 0x3303;
TIM2->CCMR1 = TIM_OC1M_VAL(TIM_OCxM_PWM_1) + TIM_CC1S_IS_OUTPUT + TIM_OC1PE ;
TIM2->CCMR2 = TIM_OC3M_VAL(TIM_OCxM_PWM_1) + TIM_CC3S_IS_OUTPUT + TIM_OC3PE +
TIM_OC4M_VAL(TIM_OCxM_PWM_1) + TIM_CC4S_IS_OUTPUT + TIM_OC4PE ;
TIM2->CCR1 = 0;
TIM2->CCR3 = 0;
TIM2->CCR4 = 0;
/* Reglage du timer 3 -> PWM pour bras bas*/
RCC->APB1ENR |= RCC_TIM3EN; /* Mise en route de l'horloge du timer 3 */
TIM3->CNT = 0; /* On cale le timer juste apres (pas de risque de se prendre une IT avant la fin de l'init) */
TIM3->PSC = 0;
TIM3->ARR = _PERIODE_PWM_TIM2_; /* Periode de PWM -> 20Khz */
TIM3->SMCR |= TIM_SMS_IS_DISABLED; /* Desactivation du SMS */
TIM3->CCER = 0x3330;
TIM3->CCMR1 = TIM_OC2M_VAL(TIM_OCxM_PWM_1) + TIM_CC2S_IS_OUTPUT + TIM_OC2PE ;
TIM3->CCMR2 = TIM_OC3M_VAL(TIM_OCxM_PWM_1) + TIM_CC3S_IS_OUTPUT + TIM_OC3PE +
TIM_OC4M_VAL(TIM_OCxM_PWM_1) + TIM_CC4S_IS_OUTPUT + TIM_OC4PE ;
TIM3->CCR2 = 0;
TIM3->CCR3 = 0;
TIM3->CCR4 = 0;
/* Regle les bras du hacheur en sortie */
/* Reglage du port A */
RCC->APB2ENR |= RCC_IOPAEN; /* Mise en route de l'horloge du port A */
GPIOA->ODR |= GPIO_PIN_0 + GPIO_PIN_2 + GPIO_PIN_3;
GPIOA->CRL &= ~((3<<GPIO_MODE_0_SHIFT) + (3<<GPIO_CNF_0_SHIFT) +
(3<<GPIO_MODE_2_SHIFT) + (3<<GPIO_CNF_2_SHIFT) +
(3<<GPIO_MODE_3_SHIFT) + (3<<GPIO_CNF_3_SHIFT));
GPIOA->CRL |= (GPIO_MODE_OUTPUT_50_MHZ<<GPIO_MODE_0_SHIFT) + (GPIO_CNF_ALTERNATE_PUSH_PULL<<GPIO_CNF_0_SHIFT) +
(GPIO_MODE_OUTPUT_50_MHZ<<GPIO_MODE_2_SHIFT) + (GPIO_CNF_ALTERNATE_PUSH_PULL<<GPIO_CNF_2_SHIFT) +
(GPIO_MODE_OUTPUT_50_MHZ<<GPIO_MODE_3_SHIFT) + (GPIO_CNF_ALTERNATE_PUSH_PULL<<GPIO_CNF_3_SHIFT);
/* Reglage du port C */
RCC->APB2ENR |= RCC_IOPCEN; /* Mise en route de l'horloge du port C */
GPIOC->ODR &= ~(GPIO_PIN_7 + GPIO_PIN_8 + GPIO_PIN_9);
GPIOC->CRL &= ~((3<<GPIO_MODE_7_SHIFT) + (3<<GPIO_CNF_7_SHIFT));
GPIOC->CRH &= ~((3<<GPIO_MODE_8_SHIFT) + (3<<GPIO_CNF_8_SHIFT) +
(3<<GPIO_MODE_9_SHIFT) + (3<<GPIO_CNF_9_SHIFT));
GPIOC->CRL |= (GPIO_MODE_OUTPUT_50_MHZ<<GPIO_MODE_7_SHIFT) + (GPIO_CNF_ALTERNATE_PUSH_PULL<<GPIO_CNF_7_SHIFT);
GPIOC->CRH |= (GPIO_MODE_OUTPUT_50_MHZ<<GPIO_MODE_8_SHIFT) + (GPIO_CNF_ALTERNATE_PUSH_PULL<<GPIO_CNF_8_SHIFT) +
(GPIO_MODE_OUTPUT_50_MHZ<<GPIO_MODE_9_SHIFT) + (GPIO_CNF_ALTERNATE_PUSH_PULL<<GPIO_CNF_9_SHIFT);
/* Remap du timer 3 sur PC7, 8 et 9 */
RCC->APB2ENR |= RCC_AFIOEN; /* Mise en route de l'horloge de l'AFIO */
/* Remap entierement le timer 3 */
AFIO->MAPR = AFIO_TIM3_FULL_REMAP<<AFIO_TIM3_REMAP_SHIFT;
TIM2->CR1 |= TIM_CEN;
TIM3->CR1 |= TIM_CEN;
/* Synchronisation des deux timers */
TIM2->CNT=0;
TIM3->CNT=0xD4-0xC9+4;
}
