CPU_INT08U BSP_Joy_GetPos (void)
{
CPU_INT32U port_val;
port_val = CSP_GPIO_Rd(CSP_GPIO_PORT_NBR_02);
if (DEF_BIT_IS_CLR(port_val, BSP_GPIO2_JOY_UP)) {
return (BSP_JOY_UP);
}
if (DEF_BIT_IS_CLR(port_val, BSP_GPIO2_JOY_DOWN)) {
return (BSP_JOY_DOWN);
}
if (DEF_BIT_IS_CLR(port_val, BSP_GPIO2_JOY_LEFT)) {
return (BSP_JOY_LEFT);
}
if (DEF_BIT_IS_CLR(port_val, BSP_GPIO2_JOY_RIGHT)) {
return (BSP_JOY_RIGHT);
}
port_val = CSP_GPIO_Rd(CSP_GPIO_PORT_NBR_00);
if (DEF_BIT_IS_CLR(port_val, BSP_GPIO0_JOY_CENTER)) {
return (BSP_JOY_CENTER);
}
return (BSP_JOY_NONE);
}
static void BSP_PLL_Init (void)
{
CPU_REG32 reg_val;
CPU_SR_ALLOC();
CPU_CRITICAL_ENTER();
/* System clock divider configuration. */
BSP_REG_SIM_CLKDIV1 = (BSP_SIM_CLKDIV1_OUTDIV1_DIV2 | /* Clock 1 divide by 2. */
BSP_SIM_CLKDIV1_OUTDIV4_DIV2); /* Clock 4 divide by 2. */
/* Multipurpose clock generator configuration. */
BSP_REG_MCG_C2 = (BSP_MCG_C2_LOCRE0 | /* Generate a reset request on a loss of ext ref clk. */
BSP_MCG_C2_RANGE_HIGH_FREQ | /* Select high freq range for the crystal oscillator. */
BSP_MCG_C2_EREFS0); /* Select oscillator as the source for the ext ref clk. */
BSP_REG_MCG_C1 = (BSP_MCG_C1_CLKS_EXT_CLK | /* Selects the ext ref clk as the clk source for MCG. */
BSP_MCG_C1_FRDIV_8); /* Divide the ext ref clk by 256 for the FLL. */
while (DEF_BIT_IS_SET(BSP_REG_MCG_S, BSP_MCG_S_IREFST)) { /* Wait for Reference clock Status bit to clear. */
;
}
do { /* Wait for clock status bits to show clock. */
reg_val = (BSP_REG_MCG_S & BSP_MCG_S_CLKST_MASK) >> 2u; /* source is ext ref clk. */
} while (reg_val != 0x2);
/* --------------------- PLL0 CFG --------------------- */
BSP_REG_MCG_C5 = BSP_MCG_C5_PRDIV0_4; /* Select PLL0 external reference divider. */
BSP_REG_MCG_C6 = (BSP_MCG_C6_PLLS | /* Select the PLL output. */
BSP_MCG_C6_CME0 | /* Enable the loss of clock monitoring circuit. */
BSP_MCG_C6_VDIV0_MUL_48);
while (DEF_BIT_IS_CLR(BSP_REG_MCG_S, BSP_MCG_S_PLLST)) { /* Wait for PLL status bit to set. */
;
}
while (DEF_BIT_IS_CLR(BSP_REG_MCG_S, BSP_MCG_S_LOCK0)) { /* Wait for LOCK bit to set. */
;
}
DEF_BIT_CLR(BSP_REG_MCG_C1, BSP_MCG_C1_CLKS_MASK); /* Clear CLKS to switch CLKS mux to PLL as MCG_OUT. */
do {
reg_val = (BSP_REG_MCG_S & BSP_MCG_S_CLKST_MASK) >> 2u;
} while (reg_val != 0x3); /* Wait for clock status bits to update. */
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Set PLLFLLSEL to select the PLL for this clk src. */
CPU_CRITICAL_EXIT();
}
static void SerialDrv_RxOctet (SERIAL_DEV *pdev,
CPU_INT08U *pdatum,
SERIAL_ERR *perr)
{
CPU_INT32U reg_val;
SERIAL_DRV_REG *p_reg;
SERIAL_DEV_CFG *p_cfg;
p_cfg = pdev->Dev_Cfg;
p_reg = (SERIAL_DRV_REG *)p_cfg->BaseAddr;
reg_val = p_reg->LSR;
/* If the receive data doesn't contain data ... */
if (DEF_BIT_IS_CLR(reg_val, SERIAL_DRV_LPCXXXX_BIT_LSR_RDR)) {
*perr = SERIAL_ERR_DRV_IO_ERR;
return;
}
/* Check for Rx errors. */
if (DEF_BIT_IS_SET_ANY(reg_val, SERIAL_DRV_LPCXXXX_BIT_LSR_RX_ERR)) {
*perr = SERIAL_ERR_DRV_IO_ERR;
return;
}
*pdatum = (CPU_INT08U)(p_reg->RBR & DEF_INT_08_MASK);
*perr = SERIAL_ERR_NONE;
}
static void SerialDrv_ISR_Handler (SERIAL_DEV *pdev,
CPU_INT08U type)
{
CPU_INT08U datum;
CPU_INT32U lsr;
CPU_INT32U iir;
CPU_INT08U iir_int_id;
SERIAL_DRV_REG *p_reg;
SERIAL_DEV_CFG *p_cfg;
(void)&type;
p_cfg = pdev->Dev_Cfg;
p_reg = (SERIAL_DRV_REG *)p_cfg->BaseAddr;
iir = p_reg->IIR; /* Read te interrupt indentification register */
/* If at least one interrupt is pending ... */
while (DEF_BIT_IS_CLR(iir, SERIAL_DRV_LPCXXXX_BIT_IIR_INT_STAT)) {
iir_int_id = (CPU_INT08U)((iir & SERIAL_DRV_LPCXXXX_MSK_IIR_INT_ID) >> 1u);
switch (iir_int_id) {
case SERIAL_DRV_LPCXXXX_BIT_IIR_INT_ID_RLS: /*Rx Line Status */
lsr = p_reg->LSR;
break;
case SERIAL_DRV_LPCXXXX_BIT_IIR_INT_ID_CTI: /* Character time-out */
case SERIAL_DRV_LPCXXXX_BIT_IIR_INT_ID_RDA: /* Rx data available */
lsr = p_reg->LSR;
if (DEF_BIT_IS_CLR(lsr, SERIAL_DRV_LPCXXXX_BIT_LSR_RX_ERR)) {
datum = (CPU_INT08U)(p_reg->RBR & DEF_INT_08_MASK);
SerialIF_Rx(pdev, datum);
}
break;
case SERIAL_DRV_LPCXXXX_BIT_IIR_INT_ID_THRE: /* Transmit Holding register */
SerialIF_Tx(pdev); /* Inform serial core of wr completion. */
break;
default:
break;
}
iir = p_reg->IIR;
}
}
static void BSP_IRC_Init (void)
{
BSP_REG_MCG_SC &= ~MCG_SC_FCRDIV_MASK; /* MCGIRCLK = (4 MHz / 1) */
BSP_REG_MCG_C2 |= MCG_C2_IRCS_MASK; /* Select Fast internal reference clock (4 MHz IRC). */
BSP_REG_MCG_C1 |= MCG_C1_IRCLKEN_MASK; /* Enable the internal reference clock for MCGIRCLK. */
while (DEF_BIT_IS_CLR(BSP_REG_MCG_S, MCG_S_IRCST_MASK)) { /* Wait for IRC source to switch. */
;
}
}
CPU_INT08U BSP_SW_Read (CPU_INT08S sw)
{
switch(sw) {
case BSP_SW_1:
if (DEF_BIT_IS_CLR(GPIOC_PDIR, BSP_GPIOC_SW_1)) {
return DEF_ON;
}
break;
case BSP_SW_2:
if (DEF_BIT_IS_CLR(GPIOC_PDIR, BSP_GPIOC_SW_2)) {
return DEF_ON;
}
break;
default:
break;
}
return DEF_OFF;
}
CPU_BOOLEAN BSP_PB_GetStatus (CPU_INT08U pb_id)
{
CPU_INT32U port_val;
CPU_BOOLEAN pb_status;
pb_status = DEF_OFF;
if (pb_id == 1u) {
port_val = CSP_GPIO_Rd(CSP_GPIO_PORT_NBR_00);
if (DEF_BIT_IS_CLR(port_val, BSP_GPIO0_BUT1)) {
pb_status = DEF_ON;
}
} else if (pb_id == 2u) {
port_val = CSP_GPIO_Rd(CSP_GPIO_PORT_NBR_02);
if (DEF_BIT_IS_CLR(port_val, BSP_GPIO2_BUT2)) {
pb_status = DEF_ON;
}
} else {
;
}
return (pb_status);
}
static void SerialDrv_TxOctet (SERIAL_DEV *pdev,
CPU_INT08U datum,
SERIAL_ERR *perr)
{
CPU_INT08U reg_val;
SERIAL_DRV_REG *p_reg;
SERIAL_DEV_CFG *p_cfg;
p_cfg = pdev->Dev_Cfg;
p_reg = (SERIAL_DRV_REG *)p_cfg->BaseAddr;
reg_val = p_reg->LSR;
if (DEF_BIT_IS_CLR(reg_val, SERIAL_DRV_LPCXXXX_BIT_LSR_THRE)) {
*perr = SERIAL_ERR_DRV_IO_ERR;
return;
}
p_reg->RBR = datum;
*perr = SERIAL_ERR_NONE;
}
void BSP_Init (void)
{
CPU_INT16U reg_to;
CPU_INT32U reg_val;
CPU_SR_ALLOC();
/* ---------------- CLOCK INITIALIZATION -------------- */
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_6 /* Set 6 cycles to acces the Flash memory. */
| BSP_MSK_FLASHCFG_RST_VAL;
/* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE); /* Set the main oscillator range */
reg_to = BSP_VAL_MAX_TO;
DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN); /* Enable the Main Oscillator */
/* Wait until the main oscillator is enabled. */
while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) { /* Configuration fail */
return;
}
BSP_REG_PCLKSEL0 = DEF_BIT_NONE; /* All peripheral clock runrs at CPU_Clk / 4 = 25 Mhz */
BSP_REG_PCLKSEL1 = DEF_BIT_NONE;
/* ------------------ PLL0 CONFIGURATION -------------- */
reg_val = (((25u - 1u) << 0u) & BSP_MSK_PLLCFG0_MSEL) /* PLL0 values M = 25 & N = 2 (see note #6) */
| ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
/* 1. Disconnect PLL0 with one feed sequence if PLL ... */
/* ... already connected. */
if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
BSP_PLL_FEED_SEQ(0u);
}
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (1u - 1u); /* 3. Change the CPU clock divider setting to speed ... */
/* ... operation without PLL0 */
BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN; /* 4. Select the main osc. as the PLL0 clock source */
BSP_REG_PLLCFG(0u) = reg_val; /* 5. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(0u) /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 6. Enable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (3u - 1u); /* 7. Change the CPU clock divider setting for ... */
/* ... operation with PLL0 */
reg_to = BSP_VAL_MAX_TO; /* 8. Wait for PLL0 to achieve lock by monitoring ... */
/* ... the PLOCK0 bit in the PLL0STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return;
}
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC); /* 9. Connect PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
/* ------------------ PLL1 CONFIGURATION -------------- */
reg_val = (((4u - 1u) << 0u) & BSP_MSK_PLLCFG1_MSEL) /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
| (((0x01u ) << 5u) & BSP_MSK_PLLCFG1_NSEL);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 1. Disconnect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_PLLCFG(1u) = reg_val; /* 3. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(1u); /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 4. Enable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
reg_to = BSP_VAL_MAX_TO; /* 5. Wait for PLL1 to achieve lock by monitoring ... */
/* ... the PLOCK1 bit in the PLL1STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return;
}
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 6. Connect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5 /* Set 5 cycles to acces the Flash memory. */
| BSP_MSK_FLASHCFG_RST_VAL;
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_LED2,
CSP_GPIO_DIR_OUT,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_01,
BSP_GPIO1_LED1,
CSP_GPIO_DIR_OUT,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_BUT1,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_02,
BSP_GPIO2_BUT2,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
BSP_LED_Off(0);
CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_02,
(BSP_GPIO2_JOY_RIGHT |
BSP_GPIO2_JOY_DOWN |
BSP_GPIO2_JOY_LEFT |
BSP_GPIO2_JOY_RIGHT),
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_JOY_CENTER,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_IntInit();
CSP_IntDisAll(CSP_INT_CTRL_NBR_MAIN);
}
static CPU_BOOLEAN BSP_CPU_Init (void)
{
CPU_INT16U reg_to;
CPU_INT32U reg_val;
CPU_SR_ALLOC();
BSP_REG_FLASHCFG = (CPU_INT32U)BSP_MSK_FLASHCFG_CLK_6; /* Set 6 cycles to acces the Flash memory (Safe setting)*/
/* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE); /* Set the main oscillator range */
reg_to = BSP_VAL_MAX_TO;
DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN); /* Enable the Main Oscillator */
/* Wait until the main oscillator is enabled. */
while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) { /* Configuration fail */
return (DEF_FAIL);
}
BSP_REG_PCLKSEL0 = DEF_BIT_NONE; /* All peripheral clock runs at CPU_Clk / 4 = 25 Mhz. */
BSP_REG_PCLKSEL1 = DEF_BIT_NONE;
/* ------------------ PLL0 CONFIGURATION -------------- */
reg_val = (((25u - 1u) << 0u) & BSP_MSK_PLLCFG0_MSEL) /* PLL0 values M = 25 & N = 2 (see note #6) */
| ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
/* 1. Disconnect PLL0 with one feed sequence if PLL ... */
/* ... already connected. */
if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
BSP_PLL_FEED_SEQ(0u);
}
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (1u - 1u); /* 3. Change the CPU clock divider setting to speed ... */
/* ... operation without PLL0 */
BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN; /* 4. Select the main osc. as the PLL0 clock source */
BSP_REG_PLLCFG(0u) = reg_val; /* 5. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(0u) /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 6. Enable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (3u - 1u); /* 7. Change the CPU clock divider setting for ... */
/* ... operation with PLL0 */
reg_to = BSP_VAL_MAX_TO; /* 8. Wait for PLL0 to achieve lock by monitoring ... */
/* ... the PLOCK0 bit in the PLL0STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return (DEF_FAIL);
}
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC); /* 9. Connect PLL0 with one feed sequence. */
BSP_PLL_FEED_SEQ(0u);
/* ------------------ PLL1 CONFIGURATION -------------- */
reg_val = (((4u - 1u) << 0u) & BSP_MSK_PLLCFG1_MSEL) /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
| (((0x01u ) << 5u) & BSP_MSK_PLLCFG1_NSEL);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 1. Disconnect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_PLLCFG(1u) = reg_val; /* 3. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(1u); /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 4. Enable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
reg_to = BSP_VAL_MAX_TO; /* 5. Wait for PLL1 to achieve lock by monitoring ... */
/* ... the PLOCK1 bit in the PLL1STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return (DEF_FAIL);
}
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 6. Connect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5 /* Set 5 cycles to access the Flash memory. */
| BSP_BIT_FLASHCFG_FETCHCFG_ALL
| BSP_BIT_FLASHCFG_DATACFG_ALL
| BSP_BIT_FLASHCFG_ACCEL_EN
| BSP_BIT_FLASHCFG_PREFETCH_ALL;
return (DEF_OK);
}
void OSMonOp (OS_MON *p_mon,
OS_TICK timeout,
void *p_arg,
OS_MON_ON_ENTER_PTR p_on_enter,
OS_MON_ON_EVAL_PTR p_on_eval,
OS_OPT opt,
OS_ERR *p_err)
{
CPU_INT32U op_res;
CPU_INT32U mon_res;
OS_PEND_LIST *p_pend_list;
OS_TCB *p_tcb;
OS_TCB *p_tcb_next;
void *p_eval_data;
CPU_BOOLEAN sched;
CPU_SR_ALLOC();
#ifdef OS_SAFETY_CRITICAL
if (p_err == DEF_NULL) {
OS_SAFETY_CRITICAL_EXCEPTION();
return;
}
#endif
#if (OS_CFG_INVALID_OS_CALLS_CHK_EN == DEF_ENABLED) /* Is the kernel running? */
if (OSRunning != OS_STATE_OS_RUNNING) {
*p_err = OS_ERR_OS_NOT_RUNNING;
return;
}
#endif
#if (OS_CFG_ARG_CHK_EN == DEF_ENABLED)
if (p_mon == DEF_NULL) { /* Validate 'p_mon' */
*p_err = OS_ERR_OBJ_PTR_NULL;
return;
}
#endif
sched = DEF_NO;
CPU_CRITICAL_ENTER();
if (p_on_enter != DEF_NULL) {
op_res = (*p_on_enter)(p_mon, p_arg);
} else {
op_res = OS_MON_RES_BLOCK | OS_MON_RES_STOP_EVAL;
}
if (DEF_BIT_IS_SET(op_res, OS_MON_RES_BLOCK) == DEF_YES) {
OS_Pend((OS_PEND_OBJ *)(p_mon), /* Block task pending on Condition Variable */
OS_TASK_PEND_ON_COND_VAR,
timeout);
sched = DEF_YES;
}
OSTCBCurPtr->MonData.p_eval_data = p_arg;
OSTCBCurPtr->MonData.p_on_eval = p_on_eval;
if (DEF_BIT_IS_CLR(op_res, OS_MON_RES_STOP_EVAL) == DEF_YES) {
p_pend_list = &p_mon->PendList;
if (p_pend_list->HeadPtr != DEF_NULL) {
p_tcb = p_pend_list->HeadPtr;
while (p_tcb != DEF_NULL) {
p_tcb_next = p_tcb->PendNextPtr;
p_on_eval = p_tcb->MonData.p_on_eval;
p_eval_data = p_tcb->MonData.p_eval_data;
if (p_on_eval != DEF_NULL) {
mon_res = (*p_on_eval)(p_mon, p_eval_data, p_arg);
} else {
mon_res = OS_MON_RES_STOP_EVAL;
}
if (DEF_BIT_IS_CLR(mon_res, OS_MON_RES_BLOCK) == DEF_YES) {
OS_Post((OS_PEND_OBJ *)(p_mon), p_tcb, DEF_NULL, 0u, 0u);
if (DEF_BIT_IS_CLR(opt, OS_OPT_POST_NO_SCHED) == DEF_YES) {
sched = DEF_YES;
}
}
if (DEF_BIT_IS_SET(mon_res, OS_MON_RES_STOP_EVAL) == DEF_YES) {
break;
}
p_tcb = p_tcb_next;
}
}
}
CPU_CRITICAL_EXIT();
if (sched == DEF_YES) {
OSSched(); /* Find the next highest priority task ready to run */
}
if (DEF_BIT_IS_SET(op_res, OS_MON_RES_BLOCK) == DEF_YES) {
CPU_CRITICAL_ENTER();
switch (OSTCBCurPtr->PendStatus) {
case OS_STATUS_PEND_OK: /* We got the monitor */
*p_err = OS_ERR_NONE;
break;
case OS_STATUS_PEND_ABORT: /* Indicate that we aborted */
*p_err = OS_ERR_PEND_ABORT;
break;
case OS_STATUS_PEND_TIMEOUT: /* Indicate that we didn't get monitor within timeout */
*p_err = OS_ERR_TIMEOUT;
break;
case OS_STATUS_PEND_DEL: /* Indicate that object pended on has been deleted */
*p_err = OS_ERR_OBJ_DEL;
break;
default:
*p_err = OS_ERR_STATUS_INVALID;
}
CPU_CRITICAL_EXIT();
} else {
*p_err = OS_ERR_NONE;
}
}
