void rcba_config(void) { u32 reg32; /* * GFX INTA -> PIRQA (MSI) * D20IP_XHCI XHCI INTA -> PIRQD (MSI) * D26IP_E2P EHCI #2 INTA -> PIRQF * D27IP_ZIP HDA INTA -> PIRQA (MSI) * D28IP_P2IP WLAN INTA -> PIRQD * D28IP_P3IP Card Reader INTB -> PIRQE * D28IP_P6IP LAN INTC -> PIRQB * D29IP_E1P EHCI #1 INTA -> PIRQD * D31IP_SIP SATA INTA -> PIRQB (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) | (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) | (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); RCBA32(D20IP) = (INTA << D20IP_XHCIIP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC); DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; /* Disable PCI bridge so MRC does not probe this bus */ reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; }
void rcba_config(void) { u32 reg32; /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P2IP ETH0 INTB -> PIRQF * D28IP_P3IP SDCARD INTC -> PIRQD * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQF * D31IP_SIP SATA INTA -> PIRQB (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQA (MSI) * * Trackpad interrupt is edge triggered and cannot be shared. * TRACKPAD -> PIRQG */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | (INTC << D28IP_P3IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; /* Disable PCI bridge so MRC does not probe this bus */ reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; }
static void rcba_config(void) { u32 reg32; /* * GFX INTA -> PIRQA (MSI) * D28IP_P3IP WLAN INTA -> PIRQB * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQF * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQA (MSI) * * TRACKPAD -> PIRQE (Edge Triggered) * TOUCHSCREEN -> PIRQG (Edge Triggered) */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P3IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; RCBA32(FD) = reg32; }
void southbridge_configure_default_intmap(void) { /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP SLOT1 INTA -> PIRQB * D28IP_P2IP SLOT2 INTB -> PIRQF * D28IP_P3IP SLOT3 INTC -> PIRQD * D28IP_P5IP SLOT5 INTC -> PIRQD * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQF * D31IP_SIP SATA INTA -> PIRQB (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQA (MSI) * */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); }
* D27IP_ZIP HDA INTA -> PIRQG (MSI) */ /* Device interrupt pin register (board specific) */ RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | (INTB << D28IP_P4IP)), RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), /* Device interrupt route registers */ RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), RCBA_END_CONFIG, }; /* Copy SPD data for on-board memory */
* GNU General Public License for more details. */ #include <stdint.h> #include <cpu/intel/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), RCBA_END_CONFIG, }; void mainboard_config_superio(void) {
/* Device interrupt pin register (board specific) */ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | (INTB << D28IP_P4IP)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)), /* Device interrupt route registers */ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */ DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */ DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */ DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */ DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */ DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */ DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */ DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */ DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),
static void rcba_config(void) { u32 reg32; /* * D31IP_TTIP THRT INTC -> PIRQC * D31IP_SIP2 SATA2 NOINT * D31IP_SMIP SMBUS INTC -> PIRQC * D31IP_SIP SATA INTB -> PIRQD (MSI) * D29IP_E1P EHCI1 INTA -> PIRQH * D28IP_P8IP Slot? INTD -> PIRQD * D28IP_P7IP PCIEx1 INTC -> PIRQC * D28IP_P6IP 1394 INTB -> PIRQB (MSI) * D28IP_P5IP GbEPHY INTA -> PIRQA * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) * D28IP_P2IP Slot? INTB -> PIRQB * D28IP_P1IP Slot? INTA -> PIRQA * D27IP_ZIP HDA INTA -> PIRQG (MSI) * D26IP_E2P EHCI2 INTA -> PIRQA * D25IP_LIP ETH0 INTA -> PIRQE (MSI) * D22IP_KTIP MEI NOINT * D22IP_IDERIP MEI NOINT * D22IP_MEI2IP MEI NOINT * D22IP_MEI1IP MEI NOINT * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) * GFX INTA -> PIRQA (MSI) * PEGx16 INTA -> PIRQA * INTB -> PIRQB * INTC -> PIRQC * INTD -> PIRQD */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTC << D31IP_SMIP) | (INTB << D31IP_SIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | (INTC << D28IP_P3IP) | (INTD << D28IP_P4IP) | (INTA << D28IP_P5IP) | (INTB << D28IP_P6IP) | (INTC << D28IP_P7IP) | (INTD << D28IP_P8IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (INTA << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); RCBA32(D20IP) = (INTA << D20IP_XHCIIP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQA, PIRQD, PIRQC, PIRQA); DIR_ROUTE(D29IR, PIRQH, PIRQD, PIRQA, PIRQC); DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D27IR, PIRQG, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D26IR, PIRQA, PIRQF, PIRQC, PIRQD); DIR_ROUTE(D25IR, PIRQE, PIRQF, PIRQG, PIRQH); DIR_ROUTE(D22IR, PIRQA, PIRQD, PIRQC, PIRQB); DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; /* Disable PCI bridge so MRC does not probe this bus */ reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; }
*/ /* Device interrupt pin register (board specific) */ RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | (INTB << D28IP_P4IP)), RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)), /* Device interrupt route registers */ RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)), /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), RCBA_END_CONFIG, };
void southbridge_configure_default_intmap(void) { /* * For the PCH internal PCI functions, provide a reasonable * default IRQ mapping that utilizes only PIRQ A to D. Higher * PIRQs are sometimes used for other on-board chips that * require an edge triggered interrupt which is not shareable. */ /* * We use a linear mapping for the pin numbers. They are not * physical pins, and thus, have no relation between the dif- * ferent devices. Only rule we must obey is that a single- * function device has to use pin A. */ RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) | (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) | (INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) | (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (INTA << D25IP_LIP); RCBA32(D22IP) = (INTA << D22IP_MEI1IP); RCBA32(D20IP) = (INTA << D20IP_XHCIIP); /* * For the PIRQ allocation the following was taken into * account: * o Interrupts of the PCIe root ports are only about * events at the ports, not downstream devices. So we * don't expect many interrupts there and ignore them. * o We don't expect to talk constantly to the ME either * so ignore that, too. Same for SMBus and the thermal * device. * o Second SATA interface is only used in non-AHCI mode * so unlikely to coexist with modern interfaces (e.g. * xHCI). * o An OS that knows USB3 will likely also know how to * use MSI. * * The functions that might matter first: * * D31IP_SIP SATA 1 -> PIRQ A (MSI capable in AHCI mode) * D31IP_SIP2 SATA 2 -> PIRQ B * D29IP_E1P EHCI 1 -> PIRQ C * D27IP_ZIP HDA -> PIRQ D (MSI capable) * D26IP_E2P EHCI 2 -> PIRQ D * D25IP_LIP GbE -> PIRQ B (MSI capable) * D20IP_XHCIIP xHCI -> PIRQ B (MSI capable) * * D31IP_TTIP Thermal -> PIRQ B * D31IP_SMIP SMBUS -> PIRQ A * D28IP_* PCIe RP -> PIRQ A-D (MSI capable) * D22IP_MEI1IP ME -> PIRQ A (MSI capable) * * Note, CPU-integrated functions seem to always use PIRQ A. */ #define _none 0 DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB); DIR_ROUTE(D29IR, PIRQC, _none, _none, _none); DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D27IR, PIRQD, _none, _none, _none); DIR_ROUTE(D26IR, PIRQD, _none, _none, _none); DIR_ROUTE(D25IR, PIRQB, _none, _none, _none); DIR_ROUTE(D22IR, PIRQA, _none, _none, _none); DIR_ROUTE(D20IR, PIRQB, _none, _none, _none); #undef _none /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); }