EE_INTERRUPT void METH(IT12handler)(void)
{
#ifdef __ndk8500_a0__
t_uint16 ret=(DMA_GET_REG(DMA_ISR_L)&CD_W) | (DMA_GET_REG(DMA_ISR_L)&CD_R);
DMA_SET_REG_32(DMA_ISR_L,DMA_ISR_H,0xFFFFFFFFUL); /* ACKNOWLEDGE IT */
#elif defined __ndk8500_ed__
t_uint16 ret=(DMA_GET_REG(DMA_ISR)&CD_W) | (DMA_GET_REG(DMA_ISR)&CD_R);
DMA_SET_REG(DMA_ISR,0xFFFFU); /* ACKNOWLEDGE IT */
#elif defined __ndk20__
t_uint16 ret = 1;
DMA_SET_REG(DMA_ISR,0x0);
#endif
printf("\n\nRM:Interrupt:: IT12handler, ret = %d\n",ret);
if(ret)
{
call_interrupt(12); // BUFFER_EOW
}
} /* End of IT12() function. */
void mtf_read_table(t_uint32 addr_in,t_uint16 *pt_dest,t_uint16 len,
t_uint16 incr,t_mtf_swap_cfg swap_cfg)
{
/* this version does not handle unaligned addr_in */
/* Only FIFO 16 is used */
t_uint16 EMU_unit_maskit_prev; /* current value of EMU_unit_maskit */
volatile __XIO t_uint16 *ptr_mtf_r = 0;
t_uint16 value;
t_uint16 current_length1 = len;
t_uint16 current_length2 = (8-(len%8))%8;
t_uint16 tfl;
t_uint32 read_value=0;
t_uint32 read_value_32 = 0;
t_uint16 pgm_dma_swap = 0;
/* start of critical code section*/
EMU_unit_maskit_prev = EMU_unit_maskit;
MMDSP_EMU_MASKIT(INTERRUPT_DISABLE);
/* Check that transfer is completed */
#ifdef T1XHV_SIA
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_R) != 0);
#else
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_R) != 0);
#endif
/* configure swap in DMA and MTF */
switch (swap_cfg)
{
case MTF_NO_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16);
break;
case MTF_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16_SWAP);
break;
case MTF_NO_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16);
break;
case MTF_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_r = (volatile __XIO t_uint16*)(MTF_BASE + MTF_R_FIFO_16_SWAP);
break;
default:
ASSERT(0);
/* other not possible */
break;
}
#ifdef T1XHV_SIA
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_R)|(pgm_dma_swap ? MTF_R : 0));
#else
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_R)|(pgm_dma_swap ? MTF_R : 0));
#endif
/* program DMA transfer */
tfl = (current_length2 + current_length1) >>2;
/* Len is 16 bit word, tfl is 64 bit word */
/* addr in must be aligned on 64 bits */
DMA_SET_MTF_READ_PARAM((addr_in&(~0x7UL)),incr,tfl);
/* start DMA transfer */
#ifdef T1XHV_SIA
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_R);
MTF_SET_REG(MTF_R_REG_ENR,0x1);
#else
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_R);
MTF_SET_REG(MTF_R_REG_ENR,0x1);
#endif
/* get all values from MTF_R Fifo */
while (current_length1--) {
value = *ptr_mtf_r; /* read from fifo */
*pt_dest++ = value; /* write to MMDSP table */
}
/* Flush the Fifo */
while (current_length2--) {
value = *ptr_mtf_r; /* read from fifo */
}
/* MTF_SET_REG(MTF_R_REG_DIR,0x1);*/
/*DMA_SET_REG(DMA_DIR_L,MTF_R);*/ /* removed according to latest HW spec */
/* end of critical code section */
/* if we were in a critical code section before this function, we remain critical*/
MMDSP_EMU_MASKIT(EMU_unit_maskit_prev);
}
void mtf_write_table(t_uint32 addr_out,t_uint16 *pt_src,t_uint16 len,
t_uint16 incr,t_mtf_swap_cfg swap_cfg)
{
t_uint16 EMU_unit_maskit_prev; /* current value of EMU_unit_maskit */
volatile __XIO t_uint16 *ptr_mtf_w = 0;
t_uint16 value;
t_uint32 read_value=0;
t_uint16 pgm_dma_swap = 0;
ASSERT((len%8) == 0); /* length must be multiple of 8,16bit word or 4,32bit word */
/* start of critical code section*/
EMU_unit_maskit_prev = EMU_unit_maskit;
MMDSP_EMU_MASKIT(INTERRUPT_DISABLE);
/* Check that transfer is completed */
#ifdef T1XHV_SIA
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_W) != 0);
#else
while((DMA_GET_REG_32(DMA_ENR_L, DMA_ENR_H) & MTF_W) != 0);
#endif
switch (swap_cfg)
{
case MTF_NO_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16);
break;
case MTF_SWAP_BYTE_NO_SWAP_WORD64 :
pgm_dma_swap = 0;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16_SWAP);
break;
case MTF_NO_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16);
break;
case MTF_SWAP_BYTE_SWAP_WORD64 :
pgm_dma_swap = 1;
ptr_mtf_w = (volatile __XIO t_uint16 *)(MTF_BASE + MTF_W_FIFO_16_SWAP);
break;
default :
ASSERT(0);
break;
/* other not possible */
}
#ifdef T1XHV_SIA
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_W)|(pgm_dma_swap ? MTF_W : 0));
#else
read_value = DMA_GET_REG_32(DMA_BSM_L, DMA_BSM_H);
DMA_SET_REG_32(DMA_BSM_L, DMA_BSM_H, (read_value & ~(t_uint32)MTF_W)|(pgm_dma_swap ? MTF_W : 0));
#endif
/* program DMA transfer */
DMA_SET_MTF_WRITE_PARAM(addr_out,incr,(len>>2));
/* start DMA transfer */
#ifdef T1XHV_SIA
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_W);
#else
DMA_SET_REG_32(DMA_ENR_L, DMA_ENR_H, MTF_W);
#endif
MTF_SET_REG(MTF_W_REG_ENR,0x1);
/* write all values to MTF_W Fifo */
while (len--)
{
value = *pt_src++; /* read from MMDSP table */
*ptr_mtf_w = value; /* write to fifo */
}
/*MTF_SET_REG(MTF_W_REG_DIR,0x1);*/
/*DMA_SET_REG(DMA_DIR,MTF_W);*/ /* removed according to latest HW spec */
/* end of critical code section */
/**
* if we were in a critical code section before this function, we
* remain critical
*/
MMDSP_EMU_MASKIT(EMU_unit_maskit_prev);
}