DIB mt_dib = { CHAN_W, DEV_MT, XFR_MT0, mt_tplt, &mt };
UNIT mt_unit[] = {
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }
};
REG mt_reg[] = {
{ BRDATA (BUF, mtxb, 8, 8, MT_MAXFR) },
{ DRDATA (BPTR, mt_bptr, 18), PV_LEFT },
{ DRDATA (BLNT, mt_blnt, 18), PV_LEFT },
{ FLDATA (XFR, xfr_req, XFR_V_MT0) },
{ ORDATA (INST, mt_inst, 24) },
{ FLDATA (EOF, mt_eof, 0) },
{ FLDATA (GAP, mt_gap, 0) },
{ FLDATA (SKIP, mt_skip, 0) },
{ DRDATA (CTIME, mt_ctime, 24), REG_NZ + PV_LEFT },
{ DRDATA (GTIME, mt_gtime, 24), REG_NZ + PV_LEFT },
{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
MT_NUMDR, PV_LEFT | REG_RO) },
{ URDATA (BOT, mt_unit[0].botf, 10, 1, 0, MT_NUMDR, REG_RO) },
{ URDATA (EOT, mt_unit[0].eotf, 10, 1, 0, MT_NUMDR, REG_RO) },
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ NULL }
};
{ UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
{ UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
{ UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) }
};
REG mt_reg[] = {
{ BRDATA (BUF, mt_xb, 16, 8, MT_MAXFR) },
{ DRDATA (BPTR, mt_bptr, 17) },
{ DRDATA (BLNT, mt_blim, 17) },
{ HRDATA (RWINT, mt_rwi, MT_NUMDR) },
{ DRDATA (TIME, mt_time, 24), PV_LEFT+REG_NZ },
{ DRDATA (CTIME, mt_ctime, 24), PV_LEFT+REG_NZ },
{ DRDATA (RWTIME, mt_rwtime, 24), PV_LEFT+REG_NZ },
{ URDATA (UST, mt_unit[0].UST, 16, 8, 0, MT_NUMDR, 0) },
{ URDATA (UCMD, mt_unit[0].UCMD, 16, 8, 0, 2 * MT_NUMDR, 0) },
{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
MT_NUMDR, PV_LEFT | REG_RO) },
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ HRDATA (DEVNO, mt_dib.dva, 12), REG_HRO },
{ NULL }
};
MTAB mt_mod[] = {
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO+
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO+
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) },
{ UDATA (&rs_svc, UNIT_FIX|UNIT_ATTABLE|UNIT_DISABLE|UNIT_AUTO+
UNIT_BUFABLE|UNIT_MUSTBUF|(RS04_DTYPE << UNIT_V_DTYPE), RS04_SIZE) }
};
REG rs_reg[] = {
{ BRDATA (CS1, rscs1, DEV_RDX, 16, RS_NUMDR) },
{ BRDATA (DA, rsda, DEV_RDX, 16, RS_NUMDR) },
{ BRDATA (DS, rsds, DEV_RDX, 16, RS_NUMDR) },
{ BRDATA (ER, rser, DEV_RDX, 16, RS_NUMDR) },
{ BRDATA (MR, rsmr, DEV_RDX, 16, RS_NUMDR) },
{ BRDATA (WLKS, rswlk, DEV_RDX, 6, RS_NUMDR) },
{ DRDATA (TIME, rs_wait, 24), REG_NZ + PV_LEFT },
{ URDATA (CAPAC, rs_unit[0].capac, 10, T_ADDR_W, 0,
RS_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (STOP_IOE, rs_stopioe, 0) },
{ NULL }
};
MTAB rs_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write lockable", "LOCKABLE", NULL },
{ (UNIT_DTYPE|UNIT_ATT), (RS03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RS03", NULL, NULL },
{ (UNIT_DTYPE|UNIT_ATT), (RS04_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RS04", NULL, NULL },
{ (UNIT_AUTO|UNIT_DTYPE|UNIT_ATT), (RS03_DTYPE << UNIT_V_DTYPE),
static t_stat ptp_reset (DEVICE *dptr);
static t_stat ptp_attach (UNIT *uptr, char *cptr);
static t_stat ptp_detach (UNIT *uptr);
static int16 ptr_dsw = 0; /* device status word */
static int32 ptr_wait = 1000; /* character read wait */
static uint8 ptr_char = 0; /* last character read */
static int32 ptp_wait = 1000; /* character punch wait */
UNIT ptr_unit[1] = {
{ UDATA (&ptr_svc, UNIT_ATTABLE, 0) },
};
REG ptr_reg[] = {
{ HRDATA (DSW, ptr_dsw, 16) }, /* device status word */
{ DRDATA (WTIME, ptr_wait, 24), PV_LEFT }, /* character read wait */
{ DRDATA (LASTCHAR, ptr_char, 8), PV_LEFT }, /* last character read */
{ NULL } };
DEVICE ptr_dev = {
"PTR", ptr_unit, ptr_reg, NULL,
1, 16, 16, 1, 16, 16,
NULL, NULL, ptr_reset,
ptr_boot, ptr_attach, ptr_detach};
UNIT ptp_unit[1] = {
{ UDATA (&ptp_svc, UNIT_ATTABLE, 0) },
};
REG ptp_reg[] = {
{ HRDATA (DSW, ptr_dsw, 16) }, /* device status word (this is the same as the reader's!) */
lp62_unit LPT unit
lp62_reg LPT register list
*/
DIB lp62_dib = { DEV_LPT, 2, &lp62_iors, { &lp62_65, &lp62_66 } };
UNIT lp62_unit = {
UDATA (&lp62_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lp62_reg[] = {
{ ORDATA (BUF, lp62_unit.buf, 8) },
{ FLDATA (INT, int_hwre[API_LPT], INT_V_LPT) },
{ FLDATA (DONE, int_hwre[API_LPT], INT_V_LPT) },
{ FLDATA (SPC, int_hwre[API_LPTSPC], INT_V_LPTSPC) },
{ DRDATA (BPTR, lp62_bp, 6) },
{ ORDATA (STATE, lp62_spc, 6), REG_HRO },
{ FLDATA (OVRPR, lp62_ovrpr, 0), REG_HRO },
{ DRDATA (POS, lp62_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, lp62_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lp62_stopioe, 0) },
{ BRDATA (LBUF, lp62_buf, 8, 8, LP62_BSIZE) },
{ ORDATA (DEVNO, lp62_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB lp62_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ 0 }
};
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, MAX_DSK_SIZE) },
};
static REG dsk_reg[] = {
{ DRDATA (DISK, current_disk, 4) },
{ BRDATA (CURTRACK, current_track, 10, 32, NUM_OF_DSK), REG_CIRC + REG_RO },
{ BRDATA (CURSECTOR, current_sector, 10, 32, NUM_OF_DSK), REG_CIRC + REG_RO },
{ BRDATA (CURBYTE, current_byte, 10, 32, NUM_OF_DSK), REG_CIRC + REG_RO },
{ BRDATA (CURFLAG, current_flag, 10, 32, NUM_OF_DSK), REG_CIRC + REG_RO },
{ BRDATA (TRACKS, tracks, 10, 8, NUM_OF_DSK), REG_CIRC },
{ DRDATA (IN9COUNT, in9_count, 4), REG_RO },
{ DRDATA (IN9MESSAGE, in9_message, 4), REG_RO },
{ DRDATA (DIRTY, dirty, 4), REG_RO },
{ DRDATA (DSKWL, warnLevelDSK, 32) },
{ BRDATA (WARNLOCK, warnLock, 10, 32, NUM_OF_DSK), REG_CIRC + REG_RO },
{ BRDATA (WARNATTACHED, warnAttached, 10, 32, NUM_OF_DSK), REG_CIRC + REG_RO },
{ DRDATA (WARNDSK10, warnDSK10, 4), REG_RO },
{ DRDATA (WARNDSK11, warnDSK11, 4), REG_RO },
{ DRDATA (WARNDSK12, warnDSK12, 4), REG_RO },
{ BRDATA (DISKBUFFER, dskbuf, 10, 8, DSK_SECTSIZE), REG_CIRC + REG_RO },
ptr_reg PTR register list
*/
DIB ptr_dib = { DEV_PTR, 1, { &ptr } };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_PTR) },
{ FLDATA (ENABLE, int_enable, INT_V_PTR) },
{ FLDATA (INT, int_req, INT_V_PTR) },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL }
};
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev },
{ 0 }
};
DEVICE ptr_dev = {
"PTR", &ptr_unit, ptr_reg, ptr_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptr_reset,
&ptr_boot, NULL, NULL,
#define CHP(ch,val) ((val) & (1 << (ch)))
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
UNIT lpt_unit = {
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 50)
};
REG lpt_reg[] = {
{ BRDATA (LBUF, lpt_buf, 8, 8, LPT_BSIZE + 1) },
{ DRDATA (BPTR, lpt_bptr, 8) },
{ HRDATA (PCTL, lpt_savctrl, 8) },
{ FLDATA (PRCHK, ind[IN_PRCHK], 0) },
{ FLDATA (PRCH9, ind[IN_PRCH9], 0) },
{ FLDATA (PRCH12, ind[IN_PRCH12], 0) },
{ FLDATA (PRBSY, ind[IN_PRBSY], 0) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ BRDATA (CCT, cct, 8, 32, CCT_LNT) },
{ DRDATA (CCTP, cct_ptr, 8), PV_LEFT },
{ DRDATA (CCTL, cct_lnt, 8), REG_RO + PV_LEFT },
{ NULL }
};
DEVICE lpt_dev = {
"LPT", &lpt_unit, lpt_reg, NULL,
1, 10, 31, 1, 8, 7,
extern t_stat op_p (uint32 dev, uint32 ch);
extern t_stat op_i (uint32 dev, uint32 ch, uint32 sh4);
extern void lgp_vm_init (void);
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit descriptor
cpu_reg CPU register list
cpu_mod CPU modifiers list
*/
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX+UNIT_IN4B+UNIT_TTSS_D, MEMSIZE) };
REG cpu_reg[] = {
{ DRDATA (C, PC, 12), REG_VMAD },
{ HRDATA (A, A, 32), REG_VMIO },
{ HRDATA (IR, IR, 32), REG_VMIO },
{ FLDATA (OVF, OVF, 0) },
{ FLDATA (TSW, t_switch, 0) },
{ FLDATA (BP32, bp32, 0) },
{ FLDATA (BP16, bp16, 0) },
{ FLDATA (BP8, bp8, 0) },
{ FLDATA (BP4, bp4, 0) },
{ FLDATA (INPST, inp_strt, 0) },
{ FLDATA (INPDN, inp_done, 0) },
{ FLDATA (OUTST, out_strt, 0) },
{ FLDATA (OUTDN, out_done, 0) },
{ DRDATA (DELAY, delay, 7) },
{ BRDATA (CQ, pcq, 16, 12, PCQ_SIZE), REG_RO + REG_CIRC },
{ HRDATA (CQP, pcq_p, 6), REG_HRO },
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
DIB lpt_dib = { CHAN_W, DEV_LPT, XFR_LPT, lpt_tplt, &lpt };
UNIT lpt_unit = {
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0)
};
REG lpt_reg[] = {
{ BRDATA (BUF, lpt_buf, 8, 8, LPT_WIDTH) },
{ DRDATA (BPTR, lpt_bptr, 8), PV_LEFT },
{ FLDATA (XFR, xfr_req, XFR_V_LPT) },
{ FLDATA (ERR, lpt_err, 0) },
{ ORDATA (STA, lpt_sta, 3) },
{ BRDATA (CCT, lpt_cct, 8, 8, CCT_LNT) },
{ DRDATA (CCTP, lpt_ccp, 8), PV_LEFT },
{ DRDATA (CCTL, lpt_ccl, 8), REG_RO + PV_LEFT },
{ ORDATA (SPCINST, lpt_spc, 24) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (CTIME, lpt_ctime, 24), REG_NZ + PV_LEFT },
{ DRDATA (PTIME, lpt_ptime, 24), REG_NZ + PV_LEFT },
{ DRDATA (STIME, lpt_stime, 24), REG_NZ + PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ NULL }
};
dli_reg DLI register list
*/
DIB dli_dib = {
IOBA_DL, IOLN_DL, &dlx_rd, &dlx_wr,
2, IVCL (DLI), VEC_DLI, { &dli_iack, &dlo_iack }
};
UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT };
REG dli_reg[] = {
{ BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) },
{ BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) },
{ GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) },
{ GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) },
{ DRDATA (LINES, dlx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dli_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dli_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, dli_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB dli_mod[] = {
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dlx_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dlx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dlx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &dlx_desc },
DIB mt_dib[] = {
{ MTD, &mtdio },
{ MTC, &mtcio }
};
#define mtd_dib mt_dib[0]
#define mtc_dib mt_dib[1]
UNIT mtd_unit = { UDATA (NULL, 0, 0) };
REG mtd_reg[] = {
{ FLDATA (FLG, mtd_flag, 0) },
{ FLDATA (FBF, mtd_flagbuf, 0) },
{ BRDATA (DBUF, mtxb, 8, 8, DBSIZE) },
{ DRDATA (BPTR, mt_ptr, DB_V_SIZE + 1) },
{ DRDATA (BMAX, mt_max, DB_V_SIZE + 1) },
{ ORDATA (DEVNO, mtd_dib.devno, 6), REG_HRO },
{ NULL }
};
MTAB mtd_mod[] = {
{ MTAB_XTD | MTAB_VDV, 1, "DEVNO", "DEVNO",
&hp_setdev, &hp_showdev, &mtd_dev },
{ 0 }
};
DEVICE mtd_dev = {
"MTD", &mtd_unit, mtd_reg, mtd_mod,
1, 10, 16, 1, 8, 8,
NULL, NULL, &mt_reset,
REG rp_reg[] = {
{ BRDATA (CS1, rpcs1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DA, rpda, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DS, rpds, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER1, rper1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (HR, rmhr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (OF, rpof, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DC, rpdc, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER2, rper2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER3, rper3, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC1, rpec1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC2, rpec2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR, rpmr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR2, rmmr2, DEV_RDX, 16, RP_NUMDR) },
{ DRDATA (STIME, rp_swait, 24), REG_NZ + PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), REG_NZ + PV_LEFT },
{ URDATA (CAPAC, rp_unit[0].capac, 10, T_ADDR_W, 0,
RP_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
{ GRDATA (CTRLTYPE, rp_dib.lnt, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB rp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rp_set_bad },
{ (UNIT_DTYPE+UNIT_ATT), (RM03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RM03", NULL, NULL },
UNIT qty_unit =
{
UDATA (&qty_svc, (UNIT_ATTABLE), 0)
} ;
REG qty_reg[] = /* ('alm_reg' should be similar to this except for device code related items) */
{
{ ORDATA (BUF, qty_unit.buf, 8) },
{ FLDATA (BUSY, dev_busy, INT_V_QTY) },
{ FLDATA (DONE, dev_done, INT_V_QTY) },
{ FLDATA (DISABLE, dev_disable, INT_V_QTY) },
{ FLDATA (INT, int_req, INT_V_QTY) },
{ FLDATA (MDMCTL, qty_mdm, 0) },
{ FLDATA (AUTODS, qty_auto, 0) },
{ DRDATA (POLLS, qty_polls, 32) },
{ NULL }
} ;
MTAB qty_mod[] =
{
{ UNIT_8B, 0, "7b", "7B", NULL },
{ UNIT_8B, UNIT_8B, "8b", "8B", NULL },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *)&qty_desc },
{ UNIT_ATT, UNIT_ATT, "connections", NULL,
NULL, &tmxr_show_summ, (void *)&qty_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *)&qty_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *)&qty_desc },
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (BUF, tti_unit.buf, 16) },
{ HRDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
1, 10, 31, 1, 16, 8,
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
DIB lpt_dib = { &lpt_chsel, &lpt_chwr };
UNIT lpt_unit = {
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_CONS+UNIT_TEXT, 0)
};
REG lpt_reg[] = {
{ ORDATA (STATE, lpt_sta, 2) },
{ ORDATA (CMD, lpt_cmd, 2) },
{ ORDATA (CHOB, lpt_chob, 36) },
{ FLDATA (CHOBV, lpt_chob_v, 0) },
{ DRDATA (BPTR, lpt_bptr, 6), PV_LEFT },
{ BRDATA (BUF, lpt_bbuf, 8, 36, LPT_BINLNT) },
{ BRDATA (EBUF, lpt_ebuf, 8, 36, LPT_ECHLNT) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TSTART, lpt_tstart, 24), PV_LEFT + REG_NZ },
{ DRDATA (TSTOP, lpt_tstop, 24), PV_LEFT + REG_NZ },
{ DRDATA (TLEFT, lpt_tleft, 24), PV_LEFT + REG_NZ },
{ DRDATA (TRIGHT, lpt_tright, 24), PV_LEFT + REG_NZ },
{ NULL }
};
MTAB lpt_mod[] = {
{ UNIT_CONS, UNIT_CONS, "default to console", "DEFAULT" },
{ UNIT_CONS, 0 , "no default device", "NODEFAULT" },
{ UNIT_48, UNIT_48, "48 character chain", "48" },
{ UNIT_48, 0, "64 character chain", "64" },
dcs_dev DCS device descriptor
dcs_unit DCS unit descriptor
dcs_reg DCS register list
dcs_mod DCS modifiers list
*/
UNIT dcs_unit = { UDATA (&dcsi_svc, UNIT_ATTABLE, 0) };
REG dcs_reg[] = {
{ BRDATA (BUF, dcs_buf, 8, 8, DCS_LINES) },
{ BRDATA (FLAGS, dcs_flg, 8, 1, DCS_LINES) },
{ FLDATA (SCNF, iosta, IOS_V_DCS) },
{ ORDATA (SCAN, dcs_scan, 5) },
{ ORDATA (SEND, dcs_send, 5) },
{ DRDATA (SBSLVL, dcs_sbs, 4), REG_HRO },
{ NULL }
};
MTAB dcs_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "SBSLVL", "SBSLVL",
&dev_set_sbs, &dev_show_sbs, (void *) &dcs_sbs },
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&dcs_vlines, &tmxr_show_lines, (void *) &dcs_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &dcs_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dcs_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dcs_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
REG rx_reg[] = {
{ ORDATA (RXCS, rx_csr, 16) },
{ ORDATA (RXDB, rx_dbr, 8) },
{ ORDATA (RXES, rx_esr, 8) },
{ ORDATA (RXERR, rx_ecode, 8) },
{ ORDATA (RXTA, rx_track, 8) },
{ ORDATA (RXSA, rx_sector, 8) },
{ ORDATA (STAPTR, rx_state, 3), REG_RO },
{ ORDATA (BUFPTR, bptr, 7) },
{ FLDATA (INT, int_req, INT_V_RX) },
{ FLDATA (ERR, rx_csr, CSR_V_ERR) },
{ FLDATA (TR, rx_csr, RXCS_V_TR) },
{ FLDATA (IE, rx_csr, CSR_V_IE) },
{ FLDATA (DONE, rx_csr, RXCS_V_DONE) },
{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
{ FLDATA (FLG0, rx_unit[0].flags, UNIT_V_WLK), REG_HRO },
{ FLDATA (FLG1, rx_unit[1].flags, UNIT_V_WLK), REG_HRO },
{ FLDATA (STOP_IOE, rx_stopioe, 0) },
{ BRDATA (**BUF, buf, 8, 8, RX_NUMBY), REG_HRO },
{ NULL } };
MTAB rx_mod[] = {
{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ 0 } };
DEVICE rx_dev = {
"RX", rx_unit, rx_reg, rx_mod,
mux_reg MUX register list
mux_mod MUX modifiers list
*/
DIB mux_dib = { -1, DEV3_GMUX, 0, NULL, &mux };
UNIT mux_unit = { UDATA (&muxi_svc, UNIT_ATTABLE, 0), MUX_INIT_POLL };
REG mux_reg[] = {
{ BRDATA (STA, mux_sta, 8, 6, MUX_LINES) },
{ BRDATA (RBUF, mux_rbuf, 8, 8, MUX_LINES) },
{ BRDATA (XBUF, mux_xbuf, 8, 8, MUX_LINES) },
{ BRDATA (INT, mux_flags, 8, 1, MUX_SCANMAX) },
{ ORDATA (SCAN, mux_scan, 7) },
{ FLDATA (SLCK, mux_slck, 0) },
{ DRDATA (TPS, mux_tps, 8), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB mux_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&mux_vlines, tmxr_show_lines, (void *) &mux_desc
},
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &mux_desc
},
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &mux_desc
},
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &mux_desc
{ FLDATA (NEXINT, nexus_req[IPL_UBA], TR_UBA) },
{ FLDATA (AIIP, uba_aiip, 0) },
{ FLDATA (UIIP, uba_uiip, 0) },
{ HRDATA (FMER, uba_fmer, 32) },
{ HRDATA (FUBAR, uba_fubar, 32) },
{ HRDATA (BRSVR0, uba_svr[0], 32) },
{ HRDATA (BRSVR1, uba_svr[1], 32) },
{ HRDATA (BRSVR2, uba_svr[2], 32) },
{ HRDATA (BRSVR3, uba_svr[3], 32) },
{ HRDATA (BRRVR4, uba_rvr[0], 32) },
{ HRDATA (BRRVR5, uba_rvr[1], 32) },
{ HRDATA (BRRVR6, uba_rvr[2], 32) },
{ HRDATA (BRRVR7, uba_rvr[3], 32) },
{ BRDATA (DPR, uba_dpr, 16, 32, 16) },
{ BRDATA (MAP, uba_map, 16, 32, 496) },
{ DRDATA (AITIME, uba_aitime, 24), PV_LEFT + REG_NZ },
{ DRDATA (UITIME, uba_uitime, 24), PV_LEFT + REG_NZ },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};
MTAB uba_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
NULL, &show_nexus },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
{ "", 0 }
};
static UNIT hdsk_unit[] = {
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) },
{ UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, HDSK_CAPACITY) }
};
static REG hdsk_reg[] = {
{ DRDATA (HDCMD, hdskLastCommand, 32), REG_RO },
{ DRDATA (HDPOS, hdskCommandPosition, 32), REG_RO },
{ DRDATA (HDDSK, selectedDisk, 32), REG_RO },
{ DRDATA (HDSEC, selectedSector, 32), REG_RO },
{ DRDATA (HDTRK, selectedTrack, 32), REG_RO },
{ DRDATA (HDDMA, selectedDMA, 32), REG_RO },
{ NULL }
};
static MTAB hdsk_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT", &set_format, &show_format, NULL },
{ UNIT_HDSK_WLK, 0, "WRTENB", "WRTENB", NULL },
{ UNIT_HDSK_WLK, UNIT_HDSK_WLK, "WRTLCK", "WRTLCK", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "GEOM", "GEOM", &set_geom, &show_geom, NULL },
{ 0 }
ptr_unit PTR unit descriptor
ptr_reg PTR register list
*/
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_IN_WAIT };
REG ptr_reg[] = {
{ ORDATA (CSR, ptr_csr, 16) },
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (INT, int_req, INT_V_PTR) },
{ FLDATA (ERR, ptr_csr, CSR_V_ERR) },
{ FLDATA (BUSY, ptr_csr, CSR_V_BUSY) },
{ FLDATA (DONE, ptr_csr, CSR_V_DONE) },
{ FLDATA (IE, ptr_csr, CSR_V_IE) },
{ DRDATA (POS, ptr_unit.pos, 31), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL } };
DEVICE ptr_dev = {
"PTR", &ptr_unit, ptr_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptr_reset,
#ifdef GAMEBOY
NULL, &ptr_attach, &ptr_detach, &ptr_identify };
#else
NULL, &ptr_attach, &ptr_detach };
#endif
/* PTP data structures
DIB tto_dib = {
IOBA_TTO, IOLN_TTO, &tto_rd, &tto_wr,
1, IVCL (TTO), VEC_TTO, { NULL }
};
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_7P, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ ORDATA (BUF, tto_unit.buf, 8) },
{ ORDATA (CSR, tto_csr, 16) },
{ FLDATA (INT, IREQ (TTO), INT_V_TTO) },
{ FLDATA (ERR, tto_csr, CSR_V_ERR) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL
},
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL
},
clk_dev CLK device descriptor
clk_unit CLK unit descriptor
clk_reg CLK register list
*/
DIB clk_dib = { DEV_CLK, INT_CLK, PI_CLK, &clk };
UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
REG clk_reg[] = {
{ ORDATA (SELECT, clk_sel, 2) },
{ FLDATA (BUSY, dev_busy, INT_V_CLK) },
{ FLDATA (DONE, dev_done, INT_V_CLK) },
{ FLDATA (DISABLE, dev_disable, INT_V_CLK) },
{ FLDATA (INT, int_req, INT_V_CLK) },
{ DRDATA (TIME0, clk_time[0], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME1, clk_time[1], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME2, clk_time[2], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME3, clk_time[3], 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS0, clk_tps[0], 6), PV_LEFT + REG_HRO },
{ NULL }
};
MTAB clk_mod[] = {
{ MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
&clk_set_freq, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",
&clk_set_freq, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "LINE", NULL,
NULL, &clk_show_freq, NULL },
{ 0 }
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
tti_mod TTI modifiers list
*/
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_KSR, 0), KBD_POLL_WAIT };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ FLDATA (IRDY, dev_done, INT_V_TTI) },
{ FLDATA (IENB, ISR, INT_V_TTI) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
1, 10, 31, 1, 8, 8,
ptr_reg PTR register list
*/
DIB ptr_dib = { PTR, IOBUS, 1, &ptrio };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (READY, dev_int, INT_V_PTR) },
{ FLDATA (ENABLE, dev_enb, INT_V_PTR) },
{ FLDATA (MOTION, ptr_motion, 0) },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ ORDATA (RSTATE, ptr_unit.STA, 2), REG_HIDDEN },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL }
};
MTAB pt_mod[] = {
{ UNIT_ATT+UNIT_ASC+UNIT_UASC, UNIT_ATT+UNIT_ASC, "ASCII", NULL },
{ UNIT_ATT+UNIT_ASC+UNIT_UASC, UNIT_ATT+UNIT_ASC+UNIT_UASC, "Unix ASCII", NULL },
{ 0 }
};
DEVICE ptr_dev = {
"PTR", &ptr_unit, ptr_reg, pt_mod,
1, 10, 31, 1, 8, 8,
DIB lpt_dib = { d_LPT, -1, v_LPT, NULL, &lpt, NULL };
UNIT lpt_unit = { UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_UC+UNIT_TEXT, 0) };
REG lpt_reg[] = {
{ HRDATA (STA, lpt_sta, 8) },
{ HRDATA (BUF, lpt_unit.buf, 7) },
{ BRDATA (DBUF, lpxb, 16, 7, LPT_WIDTH) },
{ HRDATA (DBPTR, lpt_bptr, 8) },
{ HRDATA (VFUP, lpt_vfup, 8) },
{ HRDATA (VFUL, lpt_vful, 8) },
{ BRDATA (VFUT, lpt_vfut, 16, 8, VFU_LNT) },
{ FLDATA (IREQ, int_req[l_LPT], i_LPT) },
{ FLDATA (IENB, int_enb[l_LPT], i_LPT) },
{ FLDATA (IARM, lpt_arm, 0) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (CTIME, lpt_ctime, 24), PV_LEFT },
{ DRDATA (STIME, lpt_stime, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ HRDATA (DEVNO, lpt_dib.dno, 8), REG_HRO },
{ NULL }
};
MTAB lpt_mod[] = {
{ UNIT_UC, 0, "lower case", "LC", NULL },
{ UNIT_UC, UNIT_UC, "upper case", "UC", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ 0 }
};
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (BUF, tti_unit.buf, 16) },
{ HRDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
1, 10, 31, 1, 16, 8,
tti_unit TTI unit descriptor
tti_reg TTI register list
ttx_mod TTI/TTO modifiers list
*/
DIB tti_dib = { DEV_TTI, INT_TTI, PI_TTI, &tti };
UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ FLDATA (BUSY, dev_busy, INT_V_TTI) },
{ FLDATA (DONE, dev_done, INT_V_TTI) },
{ FLDATA (DISABLE, dev_disable, INT_V_TTI) },
{ FLDATA (INT, int_req, INT_V_TTI) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB ttx_mod[] = {
{ UNIT_DASHER, 0, "ANSI", "ANSI", &ttx_setmod },
{ UNIT_DASHER, UNIT_DASHER, "Dasher", "DASHER", &ttx_setmod },
{ 0 }
} ;
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, ttx_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &tti_reset,
NULL, NULL, NULL,
mctl_dev MCTL device descriptor
mctl_unit MCTL unit list
mctl_reg MCTL register list
mctl_mod MCTL modifier list
*/
DIB mctl_dib = {
IOBA_MEM, IOLN_MEM, &mctl_rd, &mctl_wr,
1, 0, 0, { NULL }
};
UNIT mctl_unit = { UDATA (NULL, 0, 0) };
REG mctl_reg[] = {
{ DRDATA (COUNT, mctl_count, 16) },
{ BRDATA (CSR, mctl_csr, DEV_RDX, 16, MAX_MCTL_COUNT) },
{ NULL }
};
DEVICE mctl_dev = {
"MCTL", &mctl_unit, mctl_reg, NULL,
1, DEV_RDX, 20, 1, DEV_RDX, 8,
NULL, NULL, &mctl_reset,
NULL, NULL, NULL,
&mctl_dib, DEV_Q18
};
/* I/O dispatch routines */
t_stat mctl_rd (int32 *data, int32 PA, int32 access)
