void adc_pwrdown_disable(void)
{
#ifndef DRV_ADC_NOT_EXIST
#ifndef DRV_ADC_NO_PDN
#if defined(__OLD_PDN_ARCH__)
#ifdef ADC_DRVPDN_FAST
DRVPDN_DISABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
#else /*ADC_DRVPDN_FAST*/
DRVPDN_Disable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
#endif /*ADC_DRVPDN_FAST*/
#else // #if defined(__OLD_PDN_ARCH__)
#ifdef ADC_DRVPDN_FAST
DRVPDN_DISABLE2(PDN_ADC);
#else /*ADC_DRVPDN_FAST*/
//DRVPDN_Disable(PDN_ADC);
PDN_CLR(PDN_ADC);
L1SM_SleepDisable(ADCSM_handler);
#endif /*ADC_DRVPDN_FAST*/
#endif // #if defined(__OLD_PDN_ARCH__)
#endif //#ifdef DRV_ADC_NO_PDN
#endif // #ifndef DRV_ADC_NOT_EXIST
}
/*
* FUNCTION
* GPT_Start
*
* DESCRIPTION
* Start GPT timer
*
* CALLS
* It is called to start GPT timer
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_Start(kal_uint8 timerNum)
{
if (timerNum == 1)
{
DRV_Reg(GPT1_CTRL) |= GPT_CTRL_Enable;
}
if (timerNum == 2)
{
DRV_Reg(GPT2_CTRL) |= GPT_CTRL_Enable;
}
#if defined(DRV_GPT_GPT3)
if (timerNum == 3)
{
DRV_Reg(GPT3_CTRL) |= GPT3_ENABLE;
}
#endif
#ifdef GPT_DRVPDN_FAST
DRVPDN_DISABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Disable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
IRQUnmask(IRQ_GPT_CODE);
}
/*
* FUNCTION
* adc_pwrdown_disable
*
* DESCRIPTION
* This function is to disable adc power down control
*
* CALLS
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* Note that this function must be called between SaveAndSetIRQMask()
* and RestoreIRQMask().
*/
void adc_pwrdown_disable(void)
{
#ifndef DRV_ADC_NOT_EXIST
#if defined(__OLD_PDN_ARCH__)
#ifdef ADC_DRVPDN_FAST
DRVPDN_DISABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
#else /*ADC_DRVPDN_FAST*/
DRVPDN_Disable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC);
#endif /*ADC_DRVPDN_FAST*/
#else // #if defined(__OLD_PDN_ARCH__)
#ifdef ADC_DRVPDN_FAST
DRVPDN_DISABLE2(PDN_ADC);
#else /*ADC_DRVPDN_FAST*/
#if !defined(__DRV_SUPPORT_LPWR__)
PDN_CLR(PDN_ADC);
L1SM_SleepDisable(ADCSM_handler);
#else
DRVPDN_Disable(PDN_ADC);
#endif //#if !defined(__DRV_SUPPORT_LPWR__)
#endif /*ADC_DRVPDN_FAST*/
#endif // #if defined(__OLD_PDN_ARCH__)
#if defined(DRV_DIE_TO_DIE_INTERFACE)
{
kal_uint32 mask;
mask = SaveAndSetIRQMask();
auxadc_die2die_enable = KAL_TRUE;
PDN_CLR(PDN_ADC); // TP use the AuxADC PDN, make sure the PDN is disable
DRV_ADC_SetBits(ABB_WR_PATH0, F26M_CLK_EN); //enable clock for die to die interface, MT6250E1
//DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_FSM_CTRL|AUXADC_26M_CLK_CTRL); //enable clock for die to die interface, MT6250E2
DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_26M_CLK_CTRL); //enable clock for die to die interface, MT6250E2
ust_busy_wait(2);
DRV_ADC_SetBits(ABB_RSV_CON1, AUXADC_FSM_CTRL); //enable clock for die to die interface, MT6250E2
DRV_ADC_SetBits(0xa0160020,0x8000);
DRV_ADC_SetBits(ABBA_WR_PATH0, ABBA_AUX_PWDB); // enable clock for auxadc analog interface logic
DRV_ADC_SetBits(ABB_WR_PATH0, AUX_PWDB); //triggle die to die interface to send and receive auxadc data
ust_busy_wait(8);
DRV_ADC_SetBits(ABB_AUX_CON0, AUX_FIFO_CLK_EN); // auxadc fifo enable
DRV_ADC_SetBits(ABB_AUX_CON0, AUX_FIFO_EN); // auxadc fifo enable
RestoreIRQMask(mask);
}
#elif defined(DRV_DIE_TO_DIE_INTERFACE_V2)
{
DRV_ADC_SetBits(D2D_D_APC_AUX_CON1, D2D_D_F26M_AUX_EN);
DRV_ADC_SetBits(D2D_A_APC_AUD_CON1, D2D_A_AUX_EN);
DRV_ADC_Reg(D2D_A_APC_AUD_CON1);
DRV_ADC_SetBits(D2D_D_APC_AUX_CON1, D2D_D_AUX_EN|D2D_D_F26M_AUX_EN);
}
#endif
#endif // #ifndef DRV_ADC_NOT_EXIST
}
/*-----------------------------------------------------------------------*
*
* This function is to enable GPT source clock.
*
*------------------------------------------------------------------------*/
static void GPT_PDN_enable()
{
#if !defined(DRV_GPT_NO_PDN_BIT)
#if defined(__OLD_PDN_ARCH__)
#if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP)
// Clear GPT PDN bit directly
#if defined(DRV_MISC_PDN_NO_SET_CLR)
#if defined(__OLD_PDN_DEFINE__)
DRV_GPT_ClearBits(DRVPDN_CON1, DRVPDN_CON1_GPT);
//DRV_GPT_Reg(DRVPDN_CON1) &= ~DRVPDN_CON1_GPT;
#elif defined(__CLKG_DEFINE__)
#if defined(DRV_GPT_NO_GPT_CG_BIT)
;
#else // #if defined(DRV_GPT_NO_GPT_CG_BIT)
ASSERT(0);
#endif // #if defined(DRV_GPT_NO_GPT_CG_BIT)
#endif // #if defined(__OLD_PDN_DEFINE__)
#else // #if defined(DRV_MISC_PDN_NO_SET_CLR)
#if defined(__OLD_PDN_DEFINE__)
DRV_GPT_WriteReg(DRVPDN_CON1_CLR, DRVPDN_CON1_GPT);
#elif defined(__CLKG_DEFINE__)
#if defined(DRV_GPT_NO_GPT_CG_BIT)
;
#else // #if defined(DRV_GPT_NO_GPT_CG_BIT)
ASSERT(0);
#endif // #if defined(DRV_GPT_NO_GPT_CG_BIT)
#endif // #if defined(__OLD_PDN_DEFINE__)
#endif // #if defined(DRV_MISC_PDN_NO_SET_CLR)
#else // #if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP)
// We need to to hook sleep mode handler to disable MCU enter sleep mode
#if defined(__OLD_PDN_DEFINE__)
#if defined(DRV_GPT_DIRECT_SLEEP_MODE_HANDLE)
// Clear GPT PDN bit directly
#if defined(DRV_MISC_PDN_NO_SET_CLR)
DRV_GPT_ClearBits(DRVPDN_CON1, DRVPDN_CON1_GPT);
//DRV_GPT_Reg(DRVPDN_CON1) &= ~DRVPDN_CON1_GPT;
#else // #if defined(DRV_MISC_PDN_NO_SET_CLR)
DRV_GPT_WriteReg(DRVPDN_CON1_CLR, DRVPDN_CON1_GPT);
#endif // #if defined(DRV_MISC_PDN_NO_SET_CLR)
#else//#if defined(DRV_GPT_DIRECT_SLEEP_MODE_HANDLE)
#ifdef GPT_DRVPDN_FAST
DRVPDN_DISABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Disable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
#endif
#elif defined(__CLKG_DEFINE__)
#if defined(DRV_GPT_NO_GPT_CG_BIT)
#ifdef GPT_DRVPDN_FAST
// DRVPDN_DISABLE2(0,0,PDN_GPT); // TTTTTT, Temp commented for MT6268A DVT load
#else // #ifdef GPT_DRVPDN_FAST
DRVPDN_Disable(0,0,PDN_GPT);
#endif // #ifdef GPT_DRVPDN_FAST
#else // #if defined(DRV_GPT_NO_GPT_CG_BIT)
ASSERT(0); // TODO
#endif // #if defined(DRV_GPT_NO_GPT_CG_BIT)
#endif // #if defined(__OLD_PDN_DEFINE__)
#endif // #if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP)
#else //#if defined(__OLD_PDN_ARCH__)
PDN_CLR(PDN_GPT);
#endif //#if defined(__OLD_PDN_ARCH__)
#endif //#if !defined(DRV_GPT_NO_PDN_BIT)
}
