void drv_idc_init_uart(void)
{
#if defined(MT6290)
DRV_WriteReg32(BASE_ADDR_MDINFRAMISC + 0x114, DRV_Reg32(BASE_ADDR_MDINFRAMISC + 0x114) | 0x6);
DRV_WriteReg32(BASE_ADDR_MDPERIMISC + 0x114, DRV_Reg32(BASE_ADDR_MDPERIMISC + 0x114) | 0x4);
#if __FPGA__
#else
// set GPIO as default output
DRV_WriteReg32_NPW(BASE_ADDR_TOPMISC + 0x1D4, DRV_Reg32(BASE_ADDR_TOPMISC + 0x1D4) | 0x200);
#endif
#endif
#if defined(MT6595)
// Enable GPIO 29, 30 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x110, DRV_Reg32(GPIO_base + 0x110) | 0x6000);
// Select GPIO 29, 30 pull-up
DRV_WriteReg32(GPIO_base + 0x210, DRV_Reg32(GPIO_base + 0x210) | 0x6000);
#endif
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_UART_INIT_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: IDC UART Init\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
// register isr, enable RX data receive interrupt
IRQMask(MD_IRQID_IDC2ARM);
// Initialize IDC UART FIFO threshold
drv_idc_set_fifo_trigger(1);
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
DRV_WriteReg32(IDC_UART_IER, IDC_UART_IER_ERBFI);
IRQ_Register_LISR(MD_IRQID_IDC2ARM, idc_uart_lisr, "IDC_UART");
DRV_Register_HISR(DRV_IDC_HISR_ID, idc_uart_hisr);
IRQSensitivity(MD_IRQID_IDC2ARM, KAL_FALSE);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_TRUE;
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_w_ptr = 3; // 2'b11
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
// Initialize baud rate
drv_idc_set_baudrate(4000000);
// initial flags/config of IDC driver
idc_port.main_state = IDC_IN_USE;
return;
}
void mt_mempll_ssc(void)
{
#if !defined(__FPGA__)
kal_uint32 reg_val;
// MT6290(M), Not E1, Because MT6290(M)E1 has WMHEC5471
if ((DRV_Reg32(HW_CODE_VERSION) == 0x00006290) && (DRV_Reg32(HW_VERSION) != 0x0000CA00)) {
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL2) & ~(EMIDDS_FH_CTL2_FRDDS_DNLMT_MASK | EMIDDS_FH_CTL2_FRDDS_UPLMT_MASK);
if (TRUE == is_mt6290m) {
// -8%. For PCW is equal to 25MHz, down limit is 2 MHz, Up limit is 0 MHz
//reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x9E) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
// -4%. For PCW is equal to 25MHz, down limit is 2 MHz, Up limit is 0 MHz
reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x4F) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
} else {
// -8%. For PCW is equal to 27.79167MHz, down limit is 2.2 MHz, Up limit is 0 MHz
//reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0xB0) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
// -4%. For PCW is equal to 27.79167MHz, down limit is 1.1 MHz, Up limit is 0 MHz
reg_val |= EMIDDS_FH_CTL2_FRDDS_DNLMT(0x58) | EMIDDS_FH_CTL2_FRDDS_UPLMT(0x0);
}
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL2, reg_val);
// Time Step is 0.5 us, Frequency Step is ~0.1MHz
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL1) & ~(EMIDDS_FH_CTL1_EMIDDS_FRDDS_DTS_MASK | EMIDDS_FH_CTL1_EMIDDS_FRDDS_DYS_MASK);
reg_val |= EMIDDS_FH_CTL1_EMIDDS_FSM_EN | EMIDDS_FH_CTL1_EMIDDS_FRDDS_EN | \
EMIDDS_FH_CTL1_EMIDDS_FRDDS_DTS(0) | EMIDDS_FH_CTL1_EMIDDS_FRDDS_DYS(0);
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL1, reg_val);
// We need to write EMIDDS_CTL to mask sure that previous settings take effect
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_CTL) | EMIDDS_SDM_PCW_CHG;
DRV_WriteReg32_NPW(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
Data_Mem_Barrier();
}
#endif // end if !defined(__FPGA__)
}
void bl_drvgpt_set_timer(kal_uint32 num, kal_uint32 time, kal_uint32 mode, kal_uint32 prescaler)
{
ASSERT( (1 <= num) && (num <= DRV_GPT_TOTAL_COUNTER) && (time <= 0xFFFFFUL) );
BL_GPTM_BUS_CLOCK_ON();
DRV_WriteReg32(MDGPT_CNT_REG(num), time);
DRV_WriteReg32(MDGPT_PSR_REG(num), prescaler);
mode &= MDGPT_CTRL_MODE_REPEAT | MDGPT_CTRL_MODE_ONESHOT;
DRV_WriteReg32_NPW(MDGPT_CTRL_REG(num), mode);//1<<1 enable timer
}
void bl_drvgpt_stop_timer(kal_uint32 num)
{
unsigned int timer_status;
ASSERT( (num >= 1) && (DRV_GPT_TOTAL_COUNTER >= num) );
BL_GPTM_BUS_CLOCK_ON();
timer_status = DRV_Reg32(MDGPT_CTRL_REG(num));
DRV_WriteReg32_NPW(MDGPT_CTRL_REG(num), timer_status & (~MDGPT_CTRL_MODE_ENABLE));
Data_Sync_Barrier();
}
static void mt_mempll_init(void)
{
#if defined(__FPGA__)
// Set Clock, temporary solution for FPGA Version: 20120814
// Bit[3:0] 0: 1x RAMC clock
// 1: 2x RAMC clock
// Bit[11:8] 0x0: 17.25MHz
// 0x1: 18.75MHz
// 0x2: 20MHz
// 0x3: 24MHz
// 0x4: 25MHz
// 0x5: 30MHz
// 0x6: 37.5MHz
// 0x7: 40MHz
// 0x8: 34.5MHz
// 0x9: 37.5Mhz
// 0xA: 40MHz
// 0xB: 48MHz
// 0xC: 50MHz
// 0xD: 60MHz
// 0xE: 75MHz
// 0xF: 80MHz
DRV_WriteReg32(REG_MDCLKCTL_FPGA_EMICTL, 0x00000701);
#else // if !defined(__FPGA__)
unsigned int reg_val;
unsigned int pll234_fb_type;
unsigned int pll234_c0_fbksel;
unsigned int pll234_c1_fb_mck_sel;
unsigned int bypass_mempll1;
unsigned int ddrphy_multi_pll_mode;
unsigned int seal_ring_mode;
unsigned int emidds_sdm_pcw_400;
unsigned int pll234_c0_fbdiv_400;
unsigned int pll234_c1_m4pdiv_400;
unsigned int emidds_sdm_pcw_333_5;
unsigned int pll234_c0_fbdiv_333_5;
unsigned int pll234_c1_m4pdiv_333_5;
unsigned int emidds_sdm_pcw_266_5;
unsigned int pll234_c0_fbdiv_266_5;
unsigned int pll234_c1_m4pdiv_266_5;
unsigned int emidds_sdm_pcw_200;
unsigned int pll234_c0_fbdiv_200;
unsigned int pll234_c1_m4pdiv_200;
unsigned int emidds_sdm_pcw;
unsigned int pll2_c0_fbdiv;
unsigned int pll2_c1_m4pdiv;
unsigned int pll3_c0_fbdiv;
unsigned int pll3_c1_m4pdiv;
unsigned int pop_pll3_c0_fbdiv;
unsigned int pop_pll3_c1_m4pdiv;
unsigned int pll4_c0_fbdiv;
unsigned int pll4_c1_m4pdiv;
/*************************************************************
* (0) check mempll is enabled and initialize local variable.
*************************************************************/
// check MEMPLL_RDY_GATING is set to HW control mode.
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) & MEMPLL_CTL_MEMPLL_RDY_GATING;
if (0 == reg_val) {
return;
}
if (TRUE == is_mt6290m) {
bypass_mempll1 = TRUE;
// NOTE!! With MT6290M, we must use multi-pll mode, because of HW limitation.
ddrphy_multi_pll_mode = TRUE;
seal_ring_mode = FALSE;
} else {
bypass_mempll1 = TRUE;
ddrphy_multi_pll_mode = TRUE;
seal_ring_mode = FALSE;
}
if (TRUE == ddrphy_multi_pll_mode) {
// External Loop
pll234_fb_type = 1;
} else {
// Internal Loop
pll234_fb_type = 0;
}
if (1 == pll234_fb_type) {
emidds_sdm_pcw_400 = 0xf6276 << 0; // 25 MHz
pll234_c0_fbdiv_400 = 0x08 << 16;
pll234_c1_m4pdiv_400 = 0x0 << 28;
emidds_sdm_pcw_333_5 = 0x111a41 << 0; // 27.79167MHz
pll234_c0_fbdiv_333_5 = 0x06 << 16;
pll234_c1_m4pdiv_333_5 = 0x0 << 28;
emidds_sdm_pcw_266_5 = 0x106666 << 0; // 26.65MHz
pll234_c0_fbdiv_266_5 = 0x05 << 16;
pll234_c1_m4pdiv_266_5 = 0x1 << 28;
emidds_sdm_pcw_200 = 0xf6276 << 0; // 25MHz
pll234_c0_fbdiv_200 = 0x04 << 16;
pll234_c1_m4pdiv_200 = 0x1 << 28;
} else {
emidds_sdm_pcw_400 = 0xf6276 << 0; // 25 MHz
pll234_c0_fbdiv_400 = 0x10 << 16;
pll234_c1_m4pdiv_400 = 0x0 << 28;
emidds_sdm_pcw_333_5 = 0xfc975 << 0; // 25.6538MHz
pll234_c0_fbdiv_333_5 = 0x0d << 16;
pll234_c1_m4pdiv_333_5 = 0x0 << 28;
emidds_sdm_pcw_266_5 = 0xee8ba << 0; // 24.2272MHz
pll234_c0_fbdiv_266_5 = 0x16 << 16;
pll234_c1_m4pdiv_266_5 = 0x1 << 28;
emidds_sdm_pcw_200 = 0xf6276 << 0; // 25MHz
pll234_c0_fbdiv_200 = 0x10 << 16;
pll234_c1_m4pdiv_200 = 0x1 << 28;
}
// Warning for set-but-not-used.
if (emidds_sdm_pcw_400) {}
if (pll234_c0_fbdiv_400) {}
if (pll234_c1_m4pdiv_400) {}
if (emidds_sdm_pcw_333_5) {}
if (pll234_c0_fbdiv_333_5) {}
if (pll234_c1_m4pdiv_333_5) {}
if (emidds_sdm_pcw_266_5) {}
if (pll234_c0_fbdiv_266_5) {}
if (pll234_c1_m4pdiv_266_5) {}
if (emidds_sdm_pcw_200) {}
if (pll234_c0_fbdiv_200) {}
if (pll234_c1_m4pdiv_200) {}
/****************************************
* (1) Setup Common Setting
****************************************/
reg_val = PLL_C0_PREDIV | PLL_C0_POSDIV | PLL_C0_SDM_DI_EN;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL0, reg_val);
reg_val = POP_PLL_C0_PREDIV | POP_PLL_C0_POSDIV | POP_PLL_C0_SDM_DI_EN;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_CTL0, reg_val);
reg_val = PLL_C1_RESERVE1;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL1, reg_val);
reg_val = POP_PLL_C1_RESERVE1;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_CTL1, reg_val);
reg_val = PLL_C2_RESERVE | PLL_C2_DIV;
if (FALSE == bypass_mempll1) {
reg_val |= 0x04 << 24;
}
if (TRUE == seal_ring_mode) {
reg_val |= 0x10 << 24;
}
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL2, reg_val);
reg_val = POP_PLL_C2_RESERVE | POP_PLL_C2_DIV;
if (FALSE == bypass_mempll1) {
reg_val |= 0x04 << 24;
}
if (TRUE == seal_ring_mode) {
reg_val |= 0x10 << 24;
}
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_CTL2, reg_val);
reg_val = PLL_PCW_N_INFO;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_PCW, reg_val);
reg_val = POP_PLL_PCW_N_INFO;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_PCW, reg_val);
reg_val = EMIDDS_SDM_FRA_EN | EMIDDS_POSDIV;
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
if (1 == pll234_fb_type) {
// External Loop
pll234_c0_fbksel = (0x0 << 24);
} else {
// Internal Loop
pll234_c0_fbksel = (0x1 << 24);
}
reg_val = PLL2_C0_PREDIV | PLL2_C0_POSDIV | PLL2_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL0, reg_val);
reg_val = PLL3_C0_PREDIV | PLL3_C0_POSDIV | PLL3_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL0, reg_val);
reg_val = POP_PLL3_C0_PREDIV | POP_PLL3_C0_POSDIV | POP_PLL3_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0, reg_val);
reg_val = PLL4_C0_PREDIV | PLL4_C0_POSDIV | PLL4_C0_VCO_DIV_SEL;
reg_val |= pll234_c0_fbksel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL0, reg_val);
if (1 == pll234_fb_type) {
// External Loop
pll234_c1_fb_mck_sel = (0x1 << 25);
} else {
// Internal Loop
pll234_c1_fb_mck_sel = (0x0 << 25);
}
reg_val = PLL2_C1_RESERVE | PLL2_C1_REF_DL | PLL2_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, reg_val);
reg_val = PLL3_C1_RESERVE | PLL3_C1_REF_DL | PLL3_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, reg_val);
reg_val = POP_PLL3_C1_RESERVE | POP_PLL3_C1_REF_DL | POP_PLL3_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, reg_val);
reg_val = PLL4_C1_RESERVE | PLL4_C1_REF_DL | PLL4_C1_FB_DL;
reg_val |= pll234_c1_fb_mck_sel;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, reg_val);
DRV_WriteReg32(DRAMC_ACTIM0, EMI_INFO[0].dramc_actim0_val);
DRV_WriteReg32(DRAMC_DDR2CTL, EMI_INFO[0].dramc_ddr2ctl_val);
/*******************************************************************************************
* (2) Setup MEMPLL operation case & frequency, May set according to dram type & frequency
*******************************************************************************************/
if (TRUE == is_mt6290m) {
#if 1
emidds_sdm_pcw = emidds_sdm_pcw_400;
pll2_c0_fbdiv = pll234_c0_fbdiv_400;
pll2_c1_m4pdiv = pll234_c1_m4pdiv_400;
pll3_c0_fbdiv = pll234_c0_fbdiv_400;
pll3_c1_m4pdiv = pll234_c1_m4pdiv_400;
pop_pll3_c0_fbdiv = pll234_c0_fbdiv_400;
pop_pll3_c1_m4pdiv = pll234_c1_m4pdiv_400;
pll4_c0_fbdiv = pll234_c0_fbdiv_400;
pll4_c1_m4pdiv = pll234_c1_m4pdiv_400;
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
} else {
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 1
emidds_sdm_pcw = emidds_sdm_pcw_333_5;
pll2_c0_fbdiv = pll234_c0_fbdiv_333_5;
pll2_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
pll3_c0_fbdiv = pll234_c0_fbdiv_333_5;
pll3_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
pop_pll3_c0_fbdiv = pll234_c0_fbdiv_333_5;
pop_pll3_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
pll4_c0_fbdiv = pll234_c0_fbdiv_333_5;
pll4_c1_m4pdiv = pll234_c1_m4pdiv_333_5;
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
}
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_CTL) | emidds_sdm_pcw;
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL0) | pll2_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL0) | pll3_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0) | pop_pll3_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL0) | pll4_c0_fbdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL0, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL1) | pll2_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL1) | pll3_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL3_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1) | pop_pll3_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL3_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL4_CTL1) | pll4_c1_m4pdiv;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL4_CTL1, reg_val);
/*************************************
* (3) Setup MEMPLL power on sequence
*************************************/
reg_val = DRV_Reg32(DRAMC_MEMPLL_DIVIDER) | DRAMC_MEMPLL_DIVIDER_DMBYP_PLL4;
if (1 == pll234_fb_type) {
reg_val |= DRAMC_MEMPLL_DIVIDER_DMPLL2CLK_EN;
}
if (TRUE == ddrphy_multi_pll_mode) {
reg_val &= ~DRAMC_MEMPLL_DIVIDER_DMBYP_PLL3_DDRPHY;
} else {
reg_val |= DRAMC_MEMPLL_DIVIDER_DMBYP_PLL3_DDRPHY;
}
DRV_WriteReg32(DRAMC_MEMPLL_DIVIDER, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) & (~(MEMPLL_CTL_MEMPLL_SW_MEMPLL_ISO_EN));
if (TRUE == is_mt6290m) {
reg_val &= ~(MEMPLL_CTL_MEMPLL_SW_POP_MEMPLL_ISO_EN);
}
reg_val |= MEMPLL_CTL_MEMPLL_RDY_GATING;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_FH_CTL1) | EMIDDS_FH_CTL1_EMIDDS_FSM_EN;
DRV_WriteReg32(REG_MDCLKCTL_EMIDDS_FH_CTL1, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_EMIDDS_CTL) | EMIDDS_SDM_PCW_CHG;
DRV_WriteReg32_NPW(REG_MDCLKCTL_EMIDDS_CTL, reg_val);
// Delay 20 us
BL_GPT_UDELAY(20);
if (FALSE == bypass_mempll1) {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_PCW) | PCW_N_INFO_CHG;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_PCW, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_PCW) | POP_PCW_N_INFO_CHG;
DRV_WriteReg32(REG_MDCLKCTL_POP_MEMPLL_PCW, reg_val);
}
reg_val = DRV_Reg32(REG_MDCLKCTL_PLL_ON_CTL1) | PLL_ON_CTL1_SW_EMIDDS_PWR_ON;
DRV_WriteReg32_NPW(REG_MDCLKCTL_PLL_ON_CTL1, reg_val);
// Delay 30 ns
BL_GPT_UDELAY(1);
}
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL1) | PLL_C1_BIAS_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL1, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL1) | POP_PLL_C1_BIAS_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL1, reg_val);
}
// Delay 2 us
BL_GPT_UDELAY(2);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL1) | PLL_C1_BIAS_LPF_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL1, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL1) | POP_PLL_C1_BIAS_LPF_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL1, reg_val);
}
// Delay 1 ms
BL_GPT_UDELAY(1000);
if ((FALSE == bypass_mempll1) || (TRUE == seal_ring_mode)) {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL0) | PLL_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL0, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL0) | POP_PLL_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL0, reg_val);
}
// Delay 20 us
BL_GPT_UDELAY(20);
}
if (FALSE == bypass_mempll1) {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL2) | PLL_C2_DIV_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL2, reg_val);
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL_CTL2) | POP_PLL_C2_DIV_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL_CTL2, reg_val);
}
// Delay 1 us
BL_GPT_UDELAY(1);
}
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL2_CTL0) | PLL2_C0_EN;
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL2_CTL0, reg_val);
if (TRUE == ddrphy_multi_pll_mode) {
if (TRUE == is_mt6290m) {
reg_val = DRV_Reg32(REG_MDCLKCTL_POP_MEMPLL3_CTL0) | POP_PLL3_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_POP_MEMPLL3_CTL0, reg_val);
} else {
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL3_CTL0) | PLL3_C0_EN;
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL3_CTL0, reg_val);
}
}
// Delay 20 us
BL_GPT_UDELAY(20);
reg_val = DRV_Reg32(DRAMC_MEMPLL_DIVIDER) | DRAMC_MEMPLL_DIVIDER_DMPLL2CLK_EN | DRAMC_MEMPLL_DIVIDER_DMALLCLK_EN;
DRV_WriteReg32_NPW(DRAMC_MEMPLL_DIVIDER, reg_val);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) & (~MEMPLL_CTL_MEMPLL_RDY_GATING);
DRV_WriteReg32(REG_MDCLKCTL_MEMPLL_CTL, reg_val);
// Simulation is about 1.1 us
BL_GPT_UDELAY(3);
reg_val = DRV_Reg32(REG_MDCLKCTL_MEMPLL_CTL) | MEMPLL_CTL_MEMPLL_MEMPLL_HW_CTL_MODE;
if (TRUE == is_mt6290m) {
reg_val |= MEMPLL_CTL_MEMPLL_POP_MEMPLL_HW_CTL_MODE;
}
DRV_WriteReg32_NPW(REG_MDCLKCTL_MEMPLL_CTL, reg_val);
#endif // end if defined(__FPGA__)
Data_Mem_Barrier();
}
