// Write a value from the TX buffer to the TX FIFO
static void spi_buffer_tx_write(spi_t *obj)
{
int data = SPI_FILL_WORD;
dspi_command_config_t command = {0};
command.isEndOfQueue = false;
// TODO: This may be wrong
command.isChipSelectContinuous = 0;
if ((obj->tx_buff.buffer) && (obj->tx_buff.pos < obj->tx_buff.length)) {
// Load the data as either an 8-bit value or a 16-bit one
if (obj->spi.bits <= 8) {
uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos];
} else if (obj->spi.bits <= 16) {
uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
data = tx[obj->tx_buff.pos];
}
// Increment the buffer position
}
obj->tx_buff.pos++;
// Send the data
DSPI_HAL_WriteDataMastermode(obj->spi.address, &command, (uint16_t)data);
// Clear the FIFO fill request
DSPI_HAL_ClearStatusFlag(obj->spi.address, kDspiTxFifoFillRequest);
}
int spi_master_write(spi_t *obj, int value) {
// wait tx buffer empty
while(!spi_writeable(obj));
dspi_command_config_t command = {0};
command.isEndOfQueue = true;
command.isChipSelectContinuous = 0;
DSPI_HAL_WriteDataMastermode(obj->spi.address, &command, (uint16_t)value);
DSPI_HAL_ClearStatusFlag(obj->spi.address, kDspiTxFifoFillRequest);
// wait rx buffer full
while (!spi_readable(obj));
DSPI_HAL_ClearStatusFlag(obj->spi.address, kDspiRxFifoDrainRequest);
return DSPI_HAL_ReadData(obj->spi.address) & 0xff;
}
uint16_t SpiInOut(Spi_t *obj, uint16_t outData)
{
uint16_t data = 0x00;
if ((obj == NULL) || (obj->Spi) == NULL) {
while (1)
;
}
if (obj->isSlave) {
} else {
dspi_command_config_t
commandConfig =
{
.isChipSelectContinuous = false,
.whichCtar = kDspiCtar0,
.whichPcs = kDspiPcs0,
.clearTransferCount = true,
.isEndOfQueue = false
};
if (outData != 0x00) {
// Restart the transfer by stop then start again, this will clear out the shift register
DSPI_HAL_StopTransfer(obj->Spi);
// Flush the FIFOs
DSPI_HAL_SetFlushFifoCmd(obj->Spi, true, true);
// Clear status flags that may have been set from previous transfers.
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoDrainRequest);
// Clear the transfer count.
DSPI_HAL_PresetTransferCount(obj->Spi, 0);
// Start the transfer process in the hardware
DSPI_HAL_StartTransfer(obj->Spi);
// Send the data to slave.
// Write data to PUSHR
DSPI_HAL_WriteDataMastermode(obj->Spi, &commandConfig, outData);
} else {
// Restart the transfer by stop then start again, this will clear out the shift register
DSPI_HAL_StopTransfer(obj->Spi);
// Flush the FIFOs
DSPI_HAL_SetFlushFifoCmd(obj->Spi, true, true);
//Clear status flags that may have been set from previous transfers.
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoDrainRequest);
// Clear the transfer count.
DSPI_HAL_PresetTransferCount(obj->Spi, 0);
// Start the transfer process in the hardware
DSPI_HAL_StartTransfer(obj->Spi);
// Write command to PUSHR.
DSPI_HAL_WriteDataMastermode(obj->Spi, &commandConfig, 0);
// Check RFDR flag
while (DSPI_HAL_GetStatusFlag(obj->Spi, kDspiRxFifoDrainRequest) == false) {
}
// Read data from POPR
data = DSPI_HAL_ReadData(obj->Spi);
// Clear RFDR flag
DSPI_HAL_ClearStatusFlag(obj->Spi, kDspiRxFifoDrainRequest);
}
}
return data;
}
