Exemplo n.º 1
0
static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
			     uint32_t engine_id, uint32_t queue_id,
			     uint32_t (**dump)[2], uint32_t *n_regs)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
		queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
	uint32_t i = 0, reg;
#undef HQD_N_REGS
#define HQD_N_REGS (19+4+2+3+7)

	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
	if (*dump == NULL)
		return -ENOMEM;

	for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
		DUMP_REG(sdma_offset + reg);
	for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
	     reg++)
		DUMP_REG(sdma_offset + reg);
	for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI;
	     reg++)
		DUMP_REG(sdma_offset + reg);
	for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG;
	     reg++)
		DUMP_REG(sdma_offset + reg);
	for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL;
	     reg++)
		DUMP_REG(sdma_offset + reg);

	WARN_ON_ONCE(i != HQD_N_REGS);
	*n_regs = i;

	return 0;
}
Exemplo n.º 2
0
static int kgd_hqd_dump(struct kgd_dev *kgd,
			uint32_t pipe_id, uint32_t queue_id,
			uint32_t (**dump)[2], uint32_t *n_regs)
{
	struct amdgpu_device *adev = get_amdgpu_device(kgd);
	uint32_t i = 0, reg;
#define HQD_N_REGS (54+4)
#define DUMP_REG(addr) do {				\
		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\
			break;				\
		(*dump)[i][0] = (addr) << 2;		\
		(*dump)[i++][1] = RREG32(addr);		\
	} while (0)

	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
	if (*dump == NULL)
		return -ENOMEM;

	acquire_queue(kgd, pipe_id, queue_id);

	DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
	DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
	DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
	DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);

	for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++)
		DUMP_REG(reg);

	release_queue(kgd);

	WARN_ON_ONCE(i != HQD_N_REGS);
	*n_regs = i;

	return 0;
}
Exemplo n.º 3
0
void crash(avr_t* avr)
{
	DUMP_REG();
	printf("*** CYCLE %" PRI_avr_cycle_count "PC %04x\n", avr->cycle, avr->pc);

	for (int i = OLD_PC_SIZE-1; i > 0; i--) {
		int pci = (avr->trace_data->old_pci + i) & 0xf;
		printf(FONT_RED "*** %04x: %-25s RESET -%d; sp %04x\n" FONT_DEFAULT,
				avr->trace_data->old[pci].pc, avr->trace_data->codeline ? avr->trace_data->codeline[avr->trace_data->old[pci].pc>>1]->symbol : "unknown", OLD_PC_SIZE-i, avr->trace_data->old[pci].sp);
	}

	printf("Stack Ptr %04x/%04x = %d \n", _avr_sp_get(avr), avr->ramend, avr->ramend - _avr_sp_get(avr));
	DUMP_STACK();

	avr_sadly_crashed(avr, 0);
}
static int dbg_dsi_show(struct seq_file *s, void *unused)
{
    struct tegra_dc_dsi_data *dsi = s->private;
    unsigned long i = 0, j = 0;
    u32 col = 0;
    u32 base[MAX_DSI_INSTANCE] = {TEGRA_DSI_BASE, TEGRA_DSIB_BASE};

    if (!dsi->enabled) {
        seq_puts(s, "DSI controller suspended\n");
        return 0;
    }

    tegra_dc_io_start(dsi->dc);
    tegra_dsi_clk_enable(dsi);

    /* mem dd dump */
    for (i = 0; i < dsi->max_instances; i++) {
        for (col = 0, j = 0; j < 0x64; j++) {
            if (col == 0)
                seq_printf(s, "%08lX:", base[i] + 4*j);
            seq_printf(s, "%c%08lX", col == 2 ? '-' : ' ',
                       tegra_dsi_controller_readl(dsi, j, i));
            if (col == 3) {
                seq_puts(s, "\n");
                col = 0;
            } else
                col++;
        }
        seq_puts(s, "\n");
    }

#define DUMP_REG(a)	seq_printf(s, "%-45s | %#05x | %#010lx |\n", \
					#a, a, tegra_dsi_readl(dsi, a));

    DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
    DUMP_REG(DSI_INCR_SYNCPT_ERROR);
    DUMP_REG(DSI_CTXSW);
    DUMP_REG(DSI_POWER_CONTROL);
    DUMP_REG(DSI_INT_ENABLE);
    DUMP_REG(DSI_HOST_DSI_CONTROL);
    DUMP_REG(DSI_CONTROL);
    DUMP_REG(DSI_SOL_DELAY);
    DUMP_REG(DSI_MAX_THRESHOLD);
    DUMP_REG(DSI_TRIGGER);
    DUMP_REG(DSI_TX_CRC);
    DUMP_REG(DSI_STATUS);
    DUMP_REG(DSI_INIT_SEQ_CONTROL);
    DUMP_REG(DSI_INIT_SEQ_DATA_0);
    DUMP_REG(DSI_INIT_SEQ_DATA_1);
    DUMP_REG(DSI_INIT_SEQ_DATA_2);
    DUMP_REG(DSI_INIT_SEQ_DATA_3);
    DUMP_REG(DSI_INIT_SEQ_DATA_4);
    DUMP_REG(DSI_INIT_SEQ_DATA_5);
    DUMP_REG(DSI_INIT_SEQ_DATA_6);
    DUMP_REG(DSI_INIT_SEQ_DATA_7);
    DUMP_REG(DSI_PKT_SEQ_0_LO);
    DUMP_REG(DSI_PKT_SEQ_0_HI);
    DUMP_REG(DSI_PKT_SEQ_1_LO);
    DUMP_REG(DSI_PKT_SEQ_1_HI);
    DUMP_REG(DSI_PKT_SEQ_2_LO);
    DUMP_REG(DSI_PKT_SEQ_2_HI);
    DUMP_REG(DSI_PKT_SEQ_3_LO);
    DUMP_REG(DSI_PKT_SEQ_3_HI);
    DUMP_REG(DSI_PKT_SEQ_4_LO);
    DUMP_REG(DSI_PKT_SEQ_4_HI);
    DUMP_REG(DSI_PKT_SEQ_5_LO);
    DUMP_REG(DSI_PKT_SEQ_5_HI);
    DUMP_REG(DSI_DCS_CMDS);
    DUMP_REG(DSI_PKT_LEN_0_1);
    DUMP_REG(DSI_PKT_LEN_2_3);
    DUMP_REG(DSI_PKT_LEN_4_5);
    DUMP_REG(DSI_PKT_LEN_6_7);
    DUMP_REG(DSI_PHY_TIMING_0);
    DUMP_REG(DSI_PHY_TIMING_1);
    DUMP_REG(DSI_PHY_TIMING_2);
    DUMP_REG(DSI_BTA_TIMING);
    DUMP_REG(DSI_TIMEOUT_0);
    DUMP_REG(DSI_TIMEOUT_1);
    DUMP_REG(DSI_TO_TALLY);
    DUMP_REG(DSI_PAD_CONTROL);
    DUMP_REG(DSI_PAD_CONTROL_CD);
    DUMP_REG(DSI_PAD_CD_STATUS);
    DUMP_REG(DSI_VID_MODE_CONTROL);
    DUMP_REG(DSI_PAD_CONTROL_0_VS1);
    DUMP_REG(DSI_PAD_CONTROL_CD_VS1);
    DUMP_REG(DSI_PAD_CD_STATUS_VS1);
    DUMP_REG(DSI_PAD_CONTROL_1_VS1);
    DUMP_REG(DSI_PAD_CONTROL_2_VS1);
    DUMP_REG(DSI_PAD_CONTROL_3_VS1);
    DUMP_REG(DSI_PAD_CONTROL_4_VS1);
    DUMP_REG(DSI_GANGED_MODE_CONTROL);
    DUMP_REG(DSI_GANGED_MODE_START);
    DUMP_REG(DSI_GANGED_MODE_SIZE);
#undef DUMP_REG

    tegra_dsi_clk_disable(dsi);
    tegra_dc_io_end(dsi->dc);

    return 0;
}
Exemplo n.º 5
0
void
dump_trapframe(struct trapframe *tf)
{
	DUMP_REG(rdi);
	DUMP_REG(rsi);
	DUMP_REG(rdx);
	DUMP_REG(rcx);
	DUMP_REG(r8);
	DUMP_REG(r9);
	DUMP_REG(rax);
	DUMP_REG(rbx);
	DUMP_REG(rbp);
	DUMP_REG(r10);
	DUMP_REG(r11);
	DUMP_REG(r12);
	DUMP_REG(r13);
	DUMP_REG(r14);
	DUMP_REG(r15);
	DUMP_REG(trapno);
	DUMP_REG(addr);
	DUMP_REG(flags);
	DUMP_REG(err);
	DUMP_REG(rip);
	DUMP_REG(rflags);
	DUMP_REG(rsp);
	DUMP_SEG(cs);
	DUMP_SEG(ss);
	DUMP_SEG(fs);
	DUMP_SEG(gs);
	DUMP_SEG(es);
	DUMP_SEG(ds);
}
Exemplo n.º 6
0
static void _dump_regs(struct tegra_dc *dc, void *data,
		       void (* print)(void *data, const char *str))
{
	int i;
	char buff[256];

	tegra_dc_io_start(dc);
	clk_enable(dc->clk);

	DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
	DUMP_REG(DC_CMD_DISPLAY_COMMAND);
	DUMP_REG(DC_CMD_SIGNAL_RAISE);
	DUMP_REG(DC_CMD_INT_STATUS);
	DUMP_REG(DC_CMD_INT_MASK);
	DUMP_REG(DC_CMD_INT_ENABLE);
	DUMP_REG(DC_CMD_INT_TYPE);
	DUMP_REG(DC_CMD_INT_POLARITY);
	DUMP_REG(DC_CMD_SIGNAL_RAISE1);
	DUMP_REG(DC_CMD_SIGNAL_RAISE2);
	DUMP_REG(DC_CMD_SIGNAL_RAISE3);
	DUMP_REG(DC_CMD_STATE_ACCESS);
	DUMP_REG(DC_CMD_STATE_CONTROL);
	DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
	DUMP_REG(DC_CMD_REG_ACT_CONTROL);

	DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
	DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
	DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
	DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
	DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
	DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
	DUMP_REG(DC_DISP_REF_TO_SYNC);
	DUMP_REG(DC_DISP_SYNC_WIDTH);
	DUMP_REG(DC_DISP_BACK_PORCH);
	DUMP_REG(DC_DISP_DISP_ACTIVE);
	DUMP_REG(DC_DISP_FRONT_PORCH);
	DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
	DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
	DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
	DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
	DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
	DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
	DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
	DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
	DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
	DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
	DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
	DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
	DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
	DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
	DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
	DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
	DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
	DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
	DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
	DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
	DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
	DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
	DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
	DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
	DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
	DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
	DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
	DUMP_REG(DC_DISP_M0_CONTROL);
	DUMP_REG(DC_DISP_M1_CONTROL);
	DUMP_REG(DC_DISP_DI_CONTROL);
	DUMP_REG(DC_DISP_PP_CONTROL);
	DUMP_REG(DC_DISP_PP_SELECT_A);
	DUMP_REG(DC_DISP_PP_SELECT_B);
	DUMP_REG(DC_DISP_PP_SELECT_C);
	DUMP_REG(DC_DISP_PP_SELECT_D);
	DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
	DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
	DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
	DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
	DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
	DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
	DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
	DUMP_REG(DC_DISP_BORDER_COLOR);
	DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
	DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
	DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
	DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
	DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
	DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
	DUMP_REG(DC_DISP_CURSOR_START_ADDR);
	DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
	DUMP_REG(DC_DISP_CURSOR_POSITION);
	DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
	DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
	DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
	DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
	DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
	DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
	DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
	DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
	DUMP_REG(DC_DISP_DAC_CRT_CTRL);
	DUMP_REG(DC_DISP_DISP_MISC_CONTROL);


	for (i = 0; i < 3; i++) {
		print(data, "\n");
		snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
		print(data, buff);

		tegra_dc_writel(dc, WINDOW_A_SELECT << i,
				DC_CMD_DISPLAY_WINDOW_HEADER);
		DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
		DUMP_REG(DC_WIN_WIN_OPTIONS);
		DUMP_REG(DC_WIN_BYTE_SWAP);
		DUMP_REG(DC_WIN_BUFFER_CONTROL);
		DUMP_REG(DC_WIN_COLOR_DEPTH);
		DUMP_REG(DC_WIN_POSITION);
		DUMP_REG(DC_WIN_SIZE);
		DUMP_REG(DC_WIN_PRESCALED_SIZE);
		DUMP_REG(DC_WIN_H_INITIAL_DDA);
		DUMP_REG(DC_WIN_V_INITIAL_DDA);
		DUMP_REG(DC_WIN_DDA_INCREMENT);
		DUMP_REG(DC_WIN_LINE_STRIDE);
		DUMP_REG(DC_WIN_BUF_STRIDE);
		DUMP_REG(DC_WIN_UV_BUF_STRIDE);
		DUMP_REG(DC_WIN_BLEND_NOKEY);
		DUMP_REG(DC_WIN_BLEND_1WIN);
		DUMP_REG(DC_WIN_BLEND_2WIN_X);
		DUMP_REG(DC_WIN_BLEND_2WIN_Y);
		DUMP_REG(DC_WIN_BLEND_3WIN_XY);
		DUMP_REG(DC_WINBUF_START_ADDR);
		DUMP_REG(DC_WINBUF_START_ADDR_U);
		DUMP_REG(DC_WINBUF_START_ADDR_V);
		DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
		DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
		DUMP_REG(DC_WINBUF_UFLOW_STATUS);
		DUMP_REG(DC_WIN_CSC_YOF);
		DUMP_REG(DC_WIN_CSC_KYRGB);
		DUMP_REG(DC_WIN_CSC_KUR);
		DUMP_REG(DC_WIN_CSC_KVR);
		DUMP_REG(DC_WIN_CSC_KUG);
		DUMP_REG(DC_WIN_CSC_KVG);
		DUMP_REG(DC_WIN_CSC_KUB);
		DUMP_REG(DC_WIN_CSC_KVB);
	}

	clk_disable(dc->clk);
	tegra_dc_io_end(dc);
}
Exemplo n.º 7
0
static void tc358767_dsi2edp_enable(struct tegra_dc_dsi_data *dsi)
{
	struct tegra_dc_dsi2edp_data *dsi2edp = tegra_dsi_get_outdata(dsi);
	unsigned val;
	unsigned chip_id;
	int i = 0;

	if (dsi2edp && dsi2edp->dsi2edp_enabled)
		return;

	if (panel_initialized == 0) {
		gpio_direction_output(DSI_PANEL_RST_GPIO, 0);
		msleep(1);
	}

	msleep(50);
	gpio_set_value(DSI_PANEL_RST_GPIO, 1);
	msleep(2);

	mutex_lock(&dsi2edp->lock);

	/* Chip ID */
	tc358767_reg_read(dsi2edp, TC358767_CHIP_ID, &val);
	chip_id = val;
	pr_info("%s: TC358767_CHIP_ID 0x%08x\n", __func__, chip_id);

#if PRBS7_PATTERN_TEST
	pr_info("%s: TC358767 output PRBS7 pattern\n", __func__);

	/* Setup main link */
	tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x00002087);
	tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_TRAINING_CTRL, 0x00003083);
	tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CLK_PARAM, 0x00000101);

	/* Setup DP-PHY/PLLs */
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000007);
	tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x00000005);
	tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x00000005);
	tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_CLK_PLL_CTRL, 0x00000005);
	msleep(70);

	/* Reset/Enable main link */
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03001107);
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000007);
	msleep(70);
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03010007);
	msleep(70);

	/* Enable PRBS7 pattern */
	tc358767_reg_write(dsi2edp, TC358767_DP_PHY_CFG_WR, 0x00000101);
	tc358767_reg_write(dsi2edp, TC358767_DP_PHY_CFG_WR, 0x00010101);
	msleep(70);
	tc358767_reg_write(dsi2edp, TC358767_DP_PHY_CFG_WR, 0x00FF0101);
	msleep(70);

	goto finish;
#endif

#if D10_2_PATTERN_TEST
	pr_info("%s: TC358767 output D10.2 pattern\n", __func__);

	/* Setup main link */
	tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x02022087);
	tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_TRAINING_CTRL, 0x00003083);
	tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CLK_PARAM, 0x00000101);

	/* Setup DP-PHY/PLLs */
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000007);
	tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x00000005);
	tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x00000005);
	tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_CLK_PLL_CTRL, 0x00000005);
	msleep(70);

	/* Reset/Enable main link */
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03001107);
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000007);
	msleep(70);
	tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03010007);
	msleep(70);

	/* Enable D10.2 pattern */
	tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x02023105);
	msleep(70);
	tc358767_reg_write(dsi2edp, TC358767_DP_PHY_CFG_WR, 0x00FF0101);
	msleep(70);

	goto finish;
#endif

#if !(COLOR_BAR_TEST)
	pr_info("%s: TC358767 normal output\n", __func__);
#else
	pr_info("%s: TC358767 output color bar pattern\n", __func__);
#endif

	if (bowser_panel_resolution == BOWSER_RESOLUTION_FHD) {
		pr_info("%s: DSI2EDP resolution set to FHD\n", __func__);
		/* Setup main link */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x3086);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_TRAINING_CTRL, 0x0002);
		DUMP_REG(dsi2edp, TC358767_DP1_LINK_TRAINING_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CLK_PARAM, 0x0101);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_CLK_PARAM, val);

		/* Setup DP-PHY/PLLs */
		tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000007);
		usleep_range(1000, 1200);
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x05);
		usleep_range(1000, 1200);
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x05);
		usleep_range(1000, 1200);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_CLK_PLL_CTRL, 0x05);
		DUMP_REG(dsi2edp, TC358767_DP1_LINK_CLK_PLL_CTRL, val);
		msleep(40);
		tc358767_reg_write(dsi2edp,
				TC358767_STREAM_CLK_PLL_PARAM, 0x01330142);
		DUMP_REG(dsi2edp, TC358767_STREAM_CLK_PLL_PARAM, val);
		tc358767_reg_write(dsi2edp,
				TC358767_STREAM_CLK_PLL_CTRL, 0x05);
		DUMP_REG(dsi2edp, TC358767_STREAM_CLK_PLL_CTRL, val);

		/* Reset/Enable main link */
		tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03001107);
		usleep_range(1000, 1200);
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000007);
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		msleep(40);

		/* Check main channel ready */
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		tc358767_reg_read(dsi2edp, TC358767_PHY_CTRL, &val);
		while (!(val & 0x10000) && (i < 10)) {
			printk("%s: main channel isn't ready (DP_PHY_Ctrl=%x), waiting.\n", __func__, val);
			msleep(5);
			i++;
		}
		if (val & 0x10000)
			printk("%s: main channel is ready (DP_PHY_Ctrl=%x)\n", __func__, val);
		else
			printk("%s: main channel isn't ready (DP_PHY_Ctrl=%x)\n", __func__, val);

		/* Read DP Rx link capability */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG1, 0x01063F);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG1, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x01);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x09);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);

		/* Check aux channel status */
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_STATUS, val);
		tc358767_reg_read(dsi2edp, TC358767_AUX_CHANNEL_STATUS, &val);
		if (val & (0x01 << 1)) {
			pr_err("%s: timeout, TC358767_AUX_CHANNEL_STATUS 0x%x\n", __func__, val);
			goto finish;
		} else if (val & 0x00000001)
			printk(KERN_ERR "%s(): Black-out detected\n", __func__);

		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x02);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x09);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_STATUS, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA0, val);

		/* Setup link & DPRx config for training */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0100);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x020A);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_WR_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x0108);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0108);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x01);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_WR_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x08);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);

		/* Set DPCD 00102h for training pattern 1 */
		tc358767_reg_write(dsi2edp,
				TC358767_LINK_TRAINING_SINK_CONFIG, 0x21);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_SINK_CONFIG, val);
		tc358767_reg_write(dsi2edp,
				TC358767_LINK_TRAINING_LOOP_CTRL, 0xF600000D);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_LOOP_CTRL, val);

		/* Set DP0 training pattern 1 */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x3187);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);

		/* Enable DP0 to start link training */
		tc358767_reg_write(dsi2edp, TC358767_DP_CTRL, 0x01);
		DUMP_REG(dsi2edp, TC358767_DP_CTRL, val);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_STATUS, val);

		/* Set DPCD 00102h for training pattern 2 */
		tc358767_reg_write(dsi2edp,
				TC358767_LINK_TRAINING_SINK_CONFIG, 0x22);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_SINK_CONFIG, val);

		/* Set DP0 training pattern 2 */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x3287);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_STATUS, val);

		/* Clear DPCD 00102h */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0102);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x00);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_WR_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x08);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);

		/* Clear DP0 training pattern */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x1087);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);

		/* Read DPCD 0x00200-0x00204 */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0200);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x0409);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_STATUS, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA0, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA1, val);

		/* ASSR configuration, 770A(reg 0x0500[0] = 1) supports ASSR,
		 * need to check the ASSR capability for eDP panel(0x0500[1] = 0).
		 */
		if (chip_id & 0x01) {
			pr_err("%s: ASSR configuration\n", __func__);
			tc358767_reg_write(dsi2edp,
					TC358767_AUX_CHANNEL_DPCD_ADDR, 0x000D);
			tc358767_reg_write(dsi2edp,
					TC358767_AUX_CHANNEL_CONFIG0, 0x0009);
			tc358767_reg_read(dsi2edp, TC358767_AUX_CHANNEL_STATUS, &val);
			tc358767_reg_read(dsi2edp,
					TC358767_AUX_CHANNEL_DPCD_RD_DATA0, &val);

			if (val & 0x01) {
				/* Enable ASSR*/
				tc358767_reg_write(dsi2edp,
						TC358767_AUX_CHANNEL_DPCD_ADDR, 0x010A);
				tc358767_reg_write(dsi2edp,
						TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x01);
				tc358767_reg_write(dsi2edp,
						TC358767_AUX_CHANNEL_CONFIG0, 0x08);
			}
		}

#if !(COLOR_BAR_TEST)
		/* DSI0 setting */
		tc358767_reg_write(dsi2edp, TC358767_DSI0_PPI_TX_RX_TA, 0x000A000C);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_TX_RX_TA, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_LPTXTIMECNT, 0x8);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_LPTXTIMECNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D0S_CLRSIPOCOUNT, 0x0D);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D0S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D1S_CLRSIPOCOUNT, 0x0D);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D1S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D2S_CLRSIPOCOUNT, 0x0D);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D2S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D3S_CLRSIPOCOUNT, 0x0D);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D3S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_LANEENABLE, 0x1F);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_LANEENABLE, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_DSI_LANEENABLE, 0x1F);
		DUMP_REG(dsi2edp, TC358767_DSI0_DSI_LANEENABLE, val);
		tc358767_reg_write(dsi2edp, TC358767_DSI0_PPI_START, 0x01);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_START, val);
		tc358767_reg_write(dsi2edp, TC358767_DSI0_DSI_START, 0x01);
		DUMP_REG(dsi2edp, TC358767_DSI0_DSI_START, val);
#endif

		/* lcd ctrl frame size */
		tc358767_reg_write(dsi2edp, TC358767_VIDEO_FRAME_CTRL, 0x064003E0);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_CTRL, val);
		val = dsi2edp->mode->h_back_porch << 16 | dsi2edp->mode->h_sync_width;
		tc358767_reg_write(dsi2edp, TC358767_HORIZONTAL_TIME0, val);
		DUMP_REG(dsi2edp, TC358767_HORIZONTAL_TIME0, val);
		val = dsi2edp->mode->h_front_porch << 16 | dsi2edp->mode->h_active;
		tc358767_reg_write(dsi2edp, TC358767_HORIZONTAL_TIME1, val);
		DUMP_REG(dsi2edp, TC358767_HORIZONTAL_TIME1, val);
		val = dsi2edp->mode->v_back_porch << 16 | dsi2edp->mode->v_sync_width;
		tc358767_reg_write(dsi2edp, TC358767_VERTICAL_TIME0, val);
		DUMP_REG(dsi2edp, TC358767_VERTICAL_TIME0, val);
		val = dsi2edp->mode->v_front_porch << 16 | dsi2edp->mode->v_active;
		tc358767_reg_write(dsi2edp, TC358767_VERTICAL_TIME1, val);
		DUMP_REG(dsi2edp, TC358767_VERTICAL_TIME1, val);
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_UPDATE_ENABLE, 0x01);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_UPDATE_ENABLE, val);

		/* DP main stream attributes */
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_OUTPUT_DELAY, 0x002907D0);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_OUTPUT_DELAY, val);
		tc358767_reg_write(dsi2edp, TC358767_VIDEO_FRAME_SIZE, 0x045E0834);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_SIZE, val);
		tc358767_reg_write(dsi2edp, TC358767_VIDEO_FRAME_START, 0x00120050);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_START, val);
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_ACTIVE_REGION_SIZE, 0x04380780);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_ACTIVE_REGION_SIZE, val);
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_SYNC_WIDTH, 0x80028002);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_SYNC_WIDTH, val);

		/* DP flow shape & timestamp */
		tc358767_reg_write(dsi2edp, TC358767_DP_CONFIG, 0x14BF0000);
		DUMP_REG(dsi2edp, TC358767_DP_CONFIG, val);

#if COLOR_BAR_TEST
		tc358767_reg_write(dsi2edp, TC358767_D2DP_TEST_CTRL, 0x78006312);
		DUMP_REG(dsi2edp, TC358767_D2DP_TEST_CTRL, val);
#endif

		tc358767_reg_write(dsi2edp,
				TC358767_FMALUE_VIDEO_CLK_REGEN, 0x00004360);
		DUMP_REG(dsi2edp, TC358767_FMALUE_VIDEO_CLK_REGEN, val);
		tc358767_reg_write(dsi2edp,
				TC358767_NVALUE_VIDEO_CLK_REGEN, 0x00008133);
		DUMP_REG(dsi2edp, TC358767_NVALUE_VIDEO_CLK_REGEN, val);
		tc358767_reg_write(dsi2edp, TC358767_DP_CTRL, 0x41);
		DUMP_REG(dsi2edp, TC358767_DP_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP_CTRL, 0x43);
		DUMP_REG(dsi2edp, TC358767_DP_CTRL, val);

#if COLOR_BAR_TEST
		tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CTRL, 0x03);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_CTRL, val);
#else
		tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CTRL, 0x01);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_CTRL, val);
#endif

		DUMP_REG(dsi2edp, TC358767_FMALUE_VIDEO_CLK_REGEN, val);
		DUMP_REG(dsi2edp, TC358767_NVALUE_VIDEO_CLK_REGEN, val);
		DUMP_REG(dsi2edp, TC358767_MVALUE_VIDEO_CLK_REGEN, val);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_STAT, val);
		DUMP_REG(dsi2edp, TC358767_DSI_INTERRUPT_STATUS, val);
	} else {
		printk(KERN_INFO "%s(): DSI2EDP resolution set to HD\n", __func__);

		/* Setup main link */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x3082);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_TRAINING_CTRL, 0x0002);
		DUMP_REG(dsi2edp, TC358767_DP1_LINK_TRAINING_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CLK_PARAM, 0x0101);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_CLK_PARAM, val);

		/* Setup DP-PHY/PLLs */
		tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000003);
		usleep_range(1000, 1200);
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x05);
		usleep_range(1000, 1200);
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, 0x05);
		usleep_range(1000, 1200);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_CLK_PLL_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP1_LINK_CLK_PLL_CTRL, 0x05);
		DUMP_REG(dsi2edp, TC358767_DP1_LINK_CLK_PLL_CTRL, val);
		msleep(40);
		tc358767_reg_write(dsi2edp,TC358767_STREAM_CLK_PLL_PARAM, 0x00330122);
		DUMP_REG(dsi2edp, TC358767_STREAM_CLK_PLL_PARAM, val);
		tc358767_reg_write(dsi2edp,
				TC358767_STREAM_CLK_PLL_CTRL, 0x05);
		DUMP_REG(dsi2edp, TC358767_STREAM_CLK_PLL_CTRL, val);

		/* Reset/Enable main link */
		tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x13001103);
		usleep_range(1000, 1200);
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_PHY_CTRL, 0x03000003);
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		msleep(40);

		/* Check main channel ready */
		DUMP_REG(dsi2edp, TC358767_PHY_CTRL, val);
		tc358767_reg_read(dsi2edp, TC358767_PHY_CTRL, &val);
		while (!(val & 0x10000) && (i < 10)) {
			printk("%s: main channel isn't ready (DP_PHY_Ctrl=%x), waiting.\n", __func__, val);
			msleep(5);
			i++;
		}
		if (val & 0x10000)
			printk("%s: main channel is ready (DP_PHY_Ctrl=%x)\n", __func__, val);
		else
			printk("%s: main channel isn't ready (DP_PHY_Ctrl=%x)\n", __func__, val);

		/* Read DP Rx link capability */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG1, 0x01063F);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG1, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x01);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x09);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);

		/* Check aux channel status */
		tc358767_reg_read(dsi2edp, TC358767_AUX_CHANNEL_STATUS, &val);
		if (val & (0x01 << 1)) {
			pr_err("%s: timeout, TC358767_AUX_CHANNEL_STATUS 0x%x\n", __func__, val);
			goto finish;
		} else
			DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_STATUS, val);

		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x02);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x09);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_STATUS, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA0, val);

		/* Setup link & DPRx config for training */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0100);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x010A);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_WR_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x0108);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0108);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x01);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_WR_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x08);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);

		/* Set DPCD 00102h for training pattern 1 */
		tc358767_reg_write(dsi2edp,
				TC358767_LINK_TRAINING_SINK_CONFIG, 0x21);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_SINK_CONFIG, val);
		tc358767_reg_write(dsi2edp,
				TC358767_LINK_TRAINING_LOOP_CTRL, 0xF600000D);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_LOOP_CTRL, val);

		/* Set DP0 training pattern 1 */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x3183);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);

		/* Enable DP0 to start link training */
		tc358767_reg_write(dsi2edp, TC358767_DP_CTRL, 0x01);
		DUMP_REG(dsi2edp, TC358767_DP_CTRL, val);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_STATUS, val);

		/* Set DPCD 00102h for training pattern 2 */
		tc358767_reg_write(dsi2edp,
				TC358767_LINK_TRAINING_SINK_CONFIG, 0x22);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_SINK_CONFIG, val);

		/* Set DP0 training pattern 2 */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x3283);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);
		DUMP_REG(dsi2edp, TC358767_LINK_TRAINING_STATUS, val);

		/* Clear DPCD 00102h */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0102);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x00);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_WR_DATA0, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x08);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);

		/* Clear DP0 training pattern */
		tc358767_reg_write(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, 0x1083);
		DUMP_REG(dsi2edp, TC358767_DP0_LINK_TRAINING_CTRL, val);

		/* Read DPCD 0x00200-0x00204 */
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_DPCD_ADDR, 0x0200);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_ADDR, val);
		tc358767_reg_write(dsi2edp,
				TC358767_AUX_CHANNEL_CONFIG0, 0x0409);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_CONFIG0, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_STATUS, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA0, val);
		DUMP_REG(dsi2edp, TC358767_AUX_CHANNEL_DPCD_RD_DATA1, val);

		/* ASSR configuration, 770A(reg 0x0500[0] = 1) supports ASSR,
		 * need to check the ASSR capability for eDP panel(0x0500[1] = 0).
		 */
		if (chip_id & 0x01) {
			pr_err("%s: ASSR configuration\n", __func__);
			tc358767_reg_write(dsi2edp,
					TC358767_AUX_CHANNEL_DPCD_ADDR, 0x000D);
			tc358767_reg_write(dsi2edp,
					TC358767_AUX_CHANNEL_CONFIG0, 0x0009);
			tc358767_reg_read(dsi2edp, TC358767_AUX_CHANNEL_STATUS, &val);
			tc358767_reg_read(dsi2edp,
					TC358767_AUX_CHANNEL_DPCD_RD_DATA0, &val);

			if (val & 0x01) {
				/* Enable ASSR*/
				tc358767_reg_write(dsi2edp,
						TC358767_AUX_CHANNEL_DPCD_ADDR, 0x010A);
				tc358767_reg_write(dsi2edp,
						TC358767_AUX_CHANNEL_DPCD_WR_DATA0, 0x01);
				tc358767_reg_write(dsi2edp,
						TC358767_AUX_CHANNEL_CONFIG0, 0x08);
			}
		}

#if !(COLOR_BAR_TEST)
		/* DSI0 setting */
		tc358767_reg_write(dsi2edp, TC358767_DSI0_PPI_TX_RX_TA, 0x00050006);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_TX_RX_TA, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_LPTXTIMECNT, 0x4);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_LPTXTIMECNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D0S_CLRSIPOCOUNT, 0x5);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D0S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D1S_CLRSIPOCOUNT, 0x5);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D1S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D2S_CLRSIPOCOUNT, 0x5);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D2S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_D3S_CLRSIPOCOUNT, 0x5);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_D3S_CLRSIPOCOUNT, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_PPI_LANEENABLE, 0x1F);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_LANEENABLE, val);
		tc358767_reg_write(dsi2edp,
				TC358767_DSI0_DSI_LANEENABLE, 0x1F);
		DUMP_REG(dsi2edp, TC358767_DSI0_DSI_LANEENABLE, val);
		tc358767_reg_write(dsi2edp, TC358767_DSI0_PPI_START, 0x01);
		DUMP_REG(dsi2edp, TC358767_DSI0_PPI_START, val);
		tc358767_reg_write(dsi2edp, TC358767_DSI0_DSI_START, 0x01);
		DUMP_REG(dsi2edp, TC358767_DSI0_DSI_START, val);
#endif

		/* lcd ctrl frame size */
		tc358767_reg_write(dsi2edp, TC358767_VIDEO_FRAME_CTRL, 0x03E00000);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_CTRL, val);
		val = dsi2edp->mode->h_back_porch << 16 | dsi2edp->mode->h_sync_width;
		tc358767_reg_write(dsi2edp, TC358767_HORIZONTAL_TIME0, val);
		DUMP_REG(dsi2edp, TC358767_HORIZONTAL_TIME0, val);
		val = dsi2edp->mode->h_front_porch << 16 | dsi2edp->mode->h_active;
		tc358767_reg_write(dsi2edp, TC358767_HORIZONTAL_TIME1, val);
		DUMP_REG(dsi2edp, TC358767_HORIZONTAL_TIME1, val);
		val = dsi2edp->mode->v_back_porch << 16 | dsi2edp->mode->v_sync_width;
		tc358767_reg_write(dsi2edp, TC358767_VERTICAL_TIME0, val);
		DUMP_REG(dsi2edp, TC358767_VERTICAL_TIME0, val);
		val = dsi2edp->mode->v_front_porch << 16 | dsi2edp->mode->v_active;
		tc358767_reg_write(dsi2edp, TC358767_VERTICAL_TIME1, val);
		DUMP_REG(dsi2edp, TC358767_VERTICAL_TIME1, val);
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_UPDATE_ENABLE, 0x01);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_UPDATE_ENABLE, val);

		/* DP main stream attributes */
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_OUTPUT_DELAY, 0x00290574);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_OUTPUT_DELAY, val);
		tc358767_reg_write(dsi2edp, TC358767_VIDEO_FRAME_SIZE, 0x033805B2);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_SIZE, val);
		tc358767_reg_write(dsi2edp, TC358767_VIDEO_FRAME_START, 0x0026001C);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_START, val);
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_ACTIVE_REGION_SIZE, 0x03000558);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_ACTIVE_REGION_SIZE, val);
		tc358767_reg_write(dsi2edp,
				TC358767_VIDEO_FRAME_SYNC_WIDTH, 0x80028002);
		DUMP_REG(dsi2edp, TC358767_VIDEO_FRAME_SYNC_WIDTH, val);

		/* DP flow shape & timestamp */
		tc358767_reg_write(dsi2edp, TC358767_DP_CONFIG, 0x14BF0000);
		DUMP_REG(dsi2edp, TC358767_DP_CONFIG, val);

#if COLOR_BAR_TEST
		tc358767_reg_write(dsi2edp, TC358767_D2DP_TEST_CTRL, 0x78006312);
		DUMP_REG(dsi2edp, TC358767_D2DP_TEST_CTRL, val);
#endif

		tc358767_reg_write(dsi2edp,
				TC358767_FMALUE_VIDEO_CLK_REGEN, 0x0220);
		DUMP_REG(dsi2edp, TC358767_FMALUE_VIDEO_CLK_REGEN, val);
		tc358767_reg_write(dsi2edp,
				TC358767_NVALUE_VIDEO_CLK_REGEN, 0x07E9);
		DUMP_REG(dsi2edp, TC358767_NVALUE_VIDEO_CLK_REGEN, val);
		tc358767_reg_write(dsi2edp, TC358767_DP_CTRL, 0x41);
		DUMP_REG(dsi2edp, TC358767_DP_CTRL, val);
		tc358767_reg_write(dsi2edp, TC358767_DP_CTRL, 0x43);
		DUMP_REG(dsi2edp, TC358767_DP_CTRL, val);

#if COLOR_BAR_TEST
		tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CTRL, 0x03);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_CTRL, val);
#else
		tc358767_reg_write(dsi2edp, TC358767_SYSTEM_CTRL, 0x01);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_CTRL, val);
#endif

		DUMP_REG(dsi2edp, TC358767_FMALUE_VIDEO_CLK_REGEN, val);
		DUMP_REG(dsi2edp, TC358767_NVALUE_VIDEO_CLK_REGEN, val);
		DUMP_REG(dsi2edp, TC358767_MVALUE_VIDEO_CLK_REGEN, val);
		DUMP_REG(dsi2edp, TC358767_SYSTEM_STAT, val);
		DUMP_REG(dsi2edp, TC358767_DSI_INTERRUPT_STATUS, val);
	}

	dsi2edp->dsi2edp_enabled = true;
	panel_initialized = 1;

finish:
	mutex_unlock(&dsi2edp->lock);
}
Exemplo n.º 8
0
static void dump_sor_reg(struct tegra_dc_sor_data *sor)
{
#define DUMP_REG(a) printk(BIOS_INFO, "%-32s  %03x  %08x\n",		\
		#a, a, tegra_sor_readl(sor, a));

	DUMP_REG(NV_SOR_SUPER_STATE0);
	DUMP_REG(NV_SOR_SUPER_STATE1);
	DUMP_REG(NV_SOR_STATE0);
	DUMP_REG(NV_SOR_STATE1);
	DUMP_REG(NV_HEAD_STATE0(0));
	DUMP_REG(NV_HEAD_STATE0(1));
	DUMP_REG(NV_HEAD_STATE1(0));
	DUMP_REG(NV_HEAD_STATE1(1));
	DUMP_REG(NV_HEAD_STATE2(0));
	DUMP_REG(NV_HEAD_STATE2(1));
	DUMP_REG(NV_HEAD_STATE3(0));
	DUMP_REG(NV_HEAD_STATE3(1));
	DUMP_REG(NV_HEAD_STATE4(0));
	DUMP_REG(NV_HEAD_STATE4(1));
	DUMP_REG(NV_HEAD_STATE5(0));
	DUMP_REG(NV_HEAD_STATE5(1));
	DUMP_REG(NV_SOR_CRC_CNTRL);
	DUMP_REG(NV_SOR_CLK_CNTRL);
	DUMP_REG(NV_SOR_CAP);
	DUMP_REG(NV_SOR_PWR);
	DUMP_REG(NV_SOR_TEST);
	DUMP_REG(NV_SOR_PLL0);
	DUMP_REG(NV_SOR_PLL1);
	DUMP_REG(NV_SOR_PLL2);
	DUMP_REG(NV_SOR_PLL3);
	DUMP_REG(NV_SOR_CSTM);
	DUMP_REG(NV_SOR_LVDS);
	DUMP_REG(NV_SOR_CRCA);
	DUMP_REG(NV_SOR_CRCB);
	DUMP_REG(NV_SOR_SEQ_CTL);
	DUMP_REG(NV_SOR_LANE_SEQ_CTL);
	DUMP_REG(NV_SOR_SEQ_INST(0));
	DUMP_REG(NV_SOR_SEQ_INST(1));
	DUMP_REG(NV_SOR_SEQ_INST(2));
	DUMP_REG(NV_SOR_SEQ_INST(3));
	DUMP_REG(NV_SOR_SEQ_INST(4));
	DUMP_REG(NV_SOR_SEQ_INST(5));
	DUMP_REG(NV_SOR_SEQ_INST(6));
	DUMP_REG(NV_SOR_SEQ_INST(7));
	DUMP_REG(NV_SOR_SEQ_INST(8));
	DUMP_REG(NV_SOR_PWM_DIV);
	DUMP_REG(NV_SOR_PWM_CTL);
	DUMP_REG(NV_SOR_MSCHECK);
	DUMP_REG(NV_SOR_XBAR_CTRL);
	DUMP_REG(NV_SOR_DP_LINKCTL(0));
	DUMP_REG(NV_SOR_DP_LINKCTL(1));
	DUMP_REG(NV_SOR_DC(0));
	DUMP_REG(NV_SOR_DC(1));
	DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
	DUMP_REG(NV_SOR_PR(0));
	DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
	DUMP_REG(NV_SOR_POSTCURSOR(0));
	DUMP_REG(NV_SOR_DP_CONFIG(0));
	DUMP_REG(NV_SOR_DP_CONFIG(1));
	DUMP_REG(NV_SOR_DP_MN(0));
	DUMP_REG(NV_SOR_DP_MN(1));
	DUMP_REG(NV_SOR_DP_PADCTL(0));
	DUMP_REG(NV_SOR_DP_PADCTL(1));
	DUMP_REG(NV_SOR_DP_DEBUG(0));
	DUMP_REG(NV_SOR_DP_DEBUG(1));
	DUMP_REG(NV_SOR_DP_SPARE(0));
	DUMP_REG(NV_SOR_DP_SPARE(1));
	DUMP_REG(NV_SOR_DP_TPG);

	return;
}
Exemplo n.º 9
0
int show_regs()
{
	TRACE_INFO("INIT command\n\r");

	DUMP_REG(PMC, PMC, PCSR);

	DUMP_REG(PIO, PIOA, PSR);
	DUMP_REG(PIO, PIOA, OSR);
	DUMP_REG(PIO, PIOA, ABSR);

	DUMP_REG(PIO, PIOB, PSR);
	DUMP_REG(PIO, PIOB, OSR);
	DUMP_REG(PIO, PIOB, ABSR);

	DUMP_REG(PIO, PIOC, PSR);
	DUMP_REG(PIO, PIOC, OSR);
	DUMP_REG(PIO, PIOC, ABSR);

	DUMP_REG(PIO, PIOD, PSR);
	DUMP_REG(PIO, PIOD, OSR);
	DUMP_REG(PIO, PIOD, ABSR);

	DUMP_REG(PIO, PIOE, PSR);
	DUMP_REG(PIO, PIOE, OSR);
	DUMP_REG(PIO, PIOE, ABSR);


	TRACE_INFO("PMC_PCSR 0x%08x\n",(*(volatile unsigned int *) (0xFFFFFC18)));
	return 0;

}