///////////////////////////////////////////////////////////////////////[02]
int SifDeinitCmd(){
int x;
DisableIntr(INT_DMA10, &x);
ReleaseIntrHandler(INT_DMA10);
SifDeinit();
return 0;
}
void RegisterInterrupts()
{
s32 ret;
DisableIntr(0x24, (int *)&ret);
DisableIntr(0x28, (int *)&ret);
DisableIntr(0x9, (int *)&ret);
ReleaseIntrHandler(0x24);
ReleaseIntrHandler(0x28);
RegisterIntrHandler(0x24, 1, TransInterrupt, &TransIntrData[0]);
RegisterIntrHandler(0x28, 1, TransInterrupt, &TransIntrData[1]);
VoiceTransComplete[0] = 0;
VoiceTransComplete[1] = 0;
ReleaseIntrHandler(0x9);
RegisterIntrHandler(0x9, 1, Spu2Interrupt, &Spu2IntrData);
}
int _stop ( void ) {
int lState;
CpuSuspendIntr ( &lState );
DisableIntr ( IOP_IRQ_SIO2, 0 );
ReleaseIntrHandler ( IOP_IRQ_SIO2 );
CpuResumeIntr ( lState );
dmac_disable ( IOP_DMAC_SIO2in );
dmac_disable ( IOP_DMAC_SIO2out );
return GetThreadId ();
} /* end _stop */
void shutdown(void)
{
int state;
#ifndef XSIO2MAN
log_flush(1);
#endif
CpuSuspendIntr(&state);
DisableIntr(IOP_IRQ_SIO2, 0);
ReleaseIntrHandler(IOP_IRQ_SIO2);
CpuResumeIntr(state);
dmac_disable(IOP_DMAC_SIO2in);
dmac_disable(IOP_DMAC_SIO2out);
}
int _start(int argc, char *argv[])
{
iop_event_t event;
int semid, evflg, res;
if ((semid = CreateMutex(IOP_MUTEX_UNLOCKED)) < 0) {
E_PRINTF("Unable to create %s (error %d).\n", "semaphore", semid);
return 1;
}
eng_args.semid = semid;
event.attr = event.bits = 0;
if ((evflg = CreateEventFlag(&event)) < 0) {
E_PRINTF("Unable to create %s (error %d).\n", "event flag", evflg);
return 1;
}
eng_args.evflg = evflg;
CpuEnableIntr();
DisableIntr(IOP_IRQ_DMA_DEV9, NULL);
if ((res = RegisterIntrHandler(IOP_IRQ_DMA_DEV9, 1, dev9_dma_handler, &eng_args.evflg))) {
E_PRINTF("Unable to register 0x%02x intr handler (error %d).\n", IOP_IRQ_DMA_DEV9, res);
return 1;
}
_sw(_lw(0xbf801570) | 0x80, 0xbf801570);
if ((res = ata_engine_init(&eng_args)) < 0) {
E_PRINTF("Unable to initialize the %s DMA engine.\n", "ATA");
return 1;
}
if ((res = smap_engine_init(&eng_args)) < 0) {
E_PRINTF("Unable to initialize the %s DMA engine.\n", "SMAP");
return 1;
}
M_PRINTF("ATA/SMAP DMA relay module initialized.\n");
return 0;
}
static void write_thread(void *arg)
{
USE_SPD_REGS;
volatile iop_dmac_chan_t *dev9_chan = (volatile iop_dmac_chan_t *)DEV9_DMAC_BASE;
struct eng_args *args = (struct eng_args *)arg;
ata_dma_transfer_t *t = &dma_transfer;
u32 res;
while (1) {
while (SleepThread() || WaitSema(args->semid))
;
ClearEventFlag(args->evflg, 0);
dma_setup(1);
EnableIntr(IOP_IRQ_DMA_DEV9);
/* Initiate the DMA transfer. */
dev9_chan->madr = (u32)dma_buffer;
dev9_chan->bcr = ((t->size / 128) << 16) | 32;
dev9_chan->chcr = 0x01000201;
SPD_REG8(0x4e) = t->command; /* ATA command register. */
SPD_REG8(SPD_R_PIO_DIR) = 1;
SPD_REG8(SPD_R_PIO_DATA) = 0;
SPD_REG8(SPD_R_XFR_CTRL) |= 0x80;
WaitEventFlag(args->evflg, (EF_DMA_DONE|EF_ATA_DONE), 0x11, &res);
SPD_REG8(SPD_R_XFR_CTRL) &= 0x7f;
DisableIntr(IOP_IRQ_DMA_DEV9, NULL);
/* If we got the ATA end signal, force stop the transfer. */
if (res & EF_ATA_DONE)
dma_stop(1);
SignalSema(args->semid);
}
}
void sbus_intr_exit()
{
DisableIntr(IOP_IRQ_SBUS, NULL);
ReleaseIntrHandler(IOP_IRQ_SBUS);
initialized = 0;
}
///////////////////////////////////////////////////////////////////////[05]
void SifExitCmd(){
int x;
DisableIntr(INT_DMA10, &x);
ReleaseIntrHandler(INT_DMA10);
}
