bool miot_uart_dev_init(struct miot_uart_state *us) {
struct miot_uart_config *cfg = us->cfg;
if (!esp_uart_validate_config(cfg)) return false;
ETS_INTR_DISABLE(ETS_UART_INUM);
uart_div_modify(us->uart_no, UART_CLK_FREQ / cfg->baud_rate);
if (us->uart_no == 0) {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
if (cfg->swap_rxcts_txrts) {
SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
} else {
CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
}
} else {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO2_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
if (cfg->swap_rxcts_txrts) {
SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART1_PIN_SWAP);
} else {
CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART1_PIN_SWAP);
}
}
unsigned int conf0 = 0b011100; /* 8-N-1 */
if (cfg->tx_fc_ena) {
conf0 |= UART_TX_FLOW_EN;
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS);
}
WRITE_PERI_REG(UART_CONF0(us->uart_no), conf0);
unsigned int conf1 = cfg->rx_fifo_full_thresh;
conf1 |= (cfg->tx_fifo_empty_thresh << 8);
if (cfg->rx_fifo_alarm >= 0) {
conf1 |= UART_RX_TOUT_EN | ((cfg->rx_fifo_alarm & 0x7f) << 24);
}
if (cfg->rx_fc_ena && cfg->rx_fifo_fc_thresh > 0) {
/* UART_RX_FLOW_EN will be set in uart_start. */
conf1 |= ((cfg->rx_fifo_fc_thresh & 0x7f) << 16);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
}
WRITE_PERI_REG(UART_CONF1(us->uart_no), conf1);
s_us[us->uart_no] = us;
/* Start with TX and RX ints disabled. */
WRITE_PERI_REG(UART_INT_ENA(us->uart_no), UART_INFO_INTS);
ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
ETS_INTR_ENABLE(ETS_UART_INUM);
return true;
}
/******************************************************************************
* FunctionName : uart_config
* Description : Internal used function
* UART0 used for data TX/RX, RX buffer size is 0x100, interrupt enabled
* UART1 just used for debug output
* Parameters : uart_no, use UART0 or UART1 defined ahead
* Returns : NONE
*******************************************************************************/
static void ICACHE_FLASH_ATTR
uart_config(uint8 uart_no)
{
if (uart_no == UART1) {
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
//PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO2_U);
PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO2_U);
} else {
/* rcv_buff size is 0x100 */
ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, &(UartDev.rcv_buff));
PIN_PULLUP_DIS (PERIPHS_IO_MUX_U0TXD_U);
//PIN_PULLDWN_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
PIN_PULLUP_DIS (PERIPHS_IO_MUX_U0RXD_U);
//PIN_PULLDWN_DIS(PERIPHS_IO_MUX_U0RXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, 0); // FUNC_U0RXD==0
}
uart_div_modify(uart_no, UART_CLK_FREQ / UartDev.baut_rate);
if (uart_no == UART1) //UART 1 always 8 N 1
WRITE_PERI_REG(UART_CONF0(uart_no),
CALC_UARTMODE(EIGHT_BITS, NONE_BITS, ONE_STOP_BIT));
else
WRITE_PERI_REG(UART_CONF0(uart_no),
CALC_UARTMODE(UartDev.data_bits, UartDev.parity, UartDev.stop_bits));
//clear rx and tx fifo,not ready
SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
if (uart_no == UART0) {
// Configure RX interrupt conditions as follows: trigger rx-full when there are 80 characters
// in the buffer, trigger rx-timeout when the fifo is non-empty and nothing further has been
// received for 4 character periods.
// Set the hardware flow-control to trigger when the FIFO holds 100 characters, although
// we don't really expect the signals to actually be wired up to anything. It doesn't hurt
// to set the threshold here...
// We do not enable framing error interrupts 'cause they tend to cause an interrupt avalanche
// and instead just poll for them when we get a std RX interrupt.
WRITE_PERI_REG(UART_CONF1(uart_no),
((80 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) |
((100 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) |
UART_RX_FLOW_EN |
(4 & UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S |
UART_RX_TOUT_EN);
SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA);
} else {
WRITE_PERI_REG(UART_CONF1(uart_no),
((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
}
//clear all interrupt
WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff);
}
void uart_set_custom_callback(uart_process_char_t cb) {
s_custom_callback = cb;
#ifndef RTOS_SDK
ETS_UART_INTR_ATTACH(rx_isr, 0);
ETS_INTR_ENABLE(ETS_UART_INUM);
#else
_xt_isr_attach(ETS_UART_INUM, rx_isr, 0);
_xt_isr_unmask(1 << ETS_UART_INUM);
#endif
}
bool mgos_uart_hal_init(struct mgos_uart_state *us) {
/* Start with ints disabled. */
WRITE_PERI_REG(UART_INT_ENA(us->uart_no), 0);
#ifdef RTOS_SDK
_xt_isr_mask(1 << ETS_UART_INUM);
_xt_isr_attach(ETS_UART_INUM, (void *) esp_uart_isr, NULL);
#else
ETS_INTR_DISABLE(ETS_UART_INUM);
ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
#endif
return true;
}
void uart_main_init(int baud_rate) {
#ifndef RTOS_SDK
system_os_task(rx_task, TASK_PRIORITY, rx_task_queue, RXTASK_QUEUE_LEN);
#endif
if (baud_rate != 0) {
uart_div_modify(0, UART_CLK_FREQ / baud_rate);
}
#ifndef RTOS_SDK
ETS_UART_INTR_ATTACH(rx_isr, 0);
ETS_INTR_ENABLE(ETS_UART_INUM);
#else
_xt_isr_attach(ETS_UART_INUM, rx_isr, 0);
_xt_isr_unmask(1 << ETS_UART_INUM);
#endif
}
void HardwareSerial::begin(const uint32_t baud/* = 9600*/)
{
//TODO: Move to params!
UartDev.baut_rate = (UartBautRate)baud;
UartDev.parity = NONE_BITS;
UartDev.exist_parity = STICK_PARITY_DIS;
UartDev.stop_bits = ONE_STOP_BIT;
UartDev.data_bits = EIGHT_BITS;
ETS_UART_INTR_ATTACH((void*)uart0_rx_intr_handler, &(UartDev.rcv_buff));
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
uart_div_modify(uart, UART_CLK_FREQ / (UartDev.baut_rate));
WRITE_PERI_REG(UART_CONF0(uart), UartDev.exist_parity
| UartDev.parity
| (UartDev.stop_bits << UART_STOP_BIT_NUM_S)
| (UartDev.data_bits << UART_BIT_NUM_S));
//clear rx and tx fifo,not ready
SET_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST);
CLEAR_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST);
//set rx fifo trigger
WRITE_PERI_REG(UART_CONF1(uart), (UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S);
//clear all interrupt
WRITE_PERI_REG(UART_INT_CLR(uart), 0xffff);
//enable rx_interrupt
SET_PERI_REG_MASK(UART_INT_ENA(uart), UART_RXFIFO_FULL_INT_ENA);
ETS_UART_INTR_ENABLE();
delay(10);
Serial.println("\r\n"); // after SPAM :)
}
int esp_uart_init(struct esp_uart_config *cfg) {
if (cfg == NULL || !esp_uart_validate_config(cfg)) return 0;
struct esp_uart_state *us = s_us[cfg->uart_no];
if (us != NULL) {
s_us[cfg->uart_no] = NULL;
esp_uart_deinit(us);
}
us = calloc(1, sizeof(*us));
us->cfg = cfg;
cs_rbuf_init(&us->rx_buf, cfg->rx_buf_size);
cs_rbuf_init(&us->tx_buf, cfg->tx_buf_size);
ETS_INTR_DISABLE(ETS_UART_INUM);
uart_div_modify(cfg->uart_no, UART_CLK_FREQ / cfg->baud_rate);
if (cfg->uart_no == 0) {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
if (cfg->swap_rxtx_ctsrts) {
SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
} else {
CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
}
} else {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO2_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
if (cfg->swap_rxtx_ctsrts) {
SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART1_PIN_SWAP);
} else {
CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART1_PIN_SWAP);
}
}
unsigned int conf0 = 0b011100; /* 8-N-1 */
if (cfg->tx_fc_ena) {
conf0 |= UART_TX_FLOW_EN;
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS);
}
WRITE_PERI_REG(UART_CONF0(cfg->uart_no), conf0);
unsigned int conf1 = cfg->rx_fifo_full_thresh;
conf1 |= (cfg->tx_fifo_empty_thresh << 8);
if (cfg->rx_fifo_alarm >= 0) {
conf1 |= UART_RX_TOUT_EN | ((cfg->rx_fifo_alarm & 0x7f) << 24);
}
if (cfg->rx_fc_ena && cfg->rx_fifo_fc_thresh > 0) {
/* UART_RX_FLOW_EN will be set in uart_start. */
conf1 |= ((cfg->rx_fifo_fc_thresh & 0x7f) << 16);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
}
WRITE_PERI_REG(UART_CONF1(cfg->uart_no), conf1);
if (cfg->status_interval_ms > 0) {
os_timer_disarm(&us->status_timer);
os_timer_setfn(&us->status_timer, esp_uart_print_status, us);
os_timer_arm(&us->status_timer, cfg->status_interval_ms, 1 /* repeat */);
}
s_us[cfg->uart_no] = us;
/* Start with TX and RX ints disabled. */
WRITE_PERI_REG(UART_INT_ENA(cfg->uart_no), UART_INFO_INTS);
ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
ETS_INTR_ENABLE(ETS_UART_INUM);
return 1;
}
