VOID
PciWrite32 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register,
UINT32 Data
)
/*++
Routine Description:
Perform an four byte PCI config cycle write
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Data - Data to write
Returns:
NONE
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return ;
}
EfiIoWrite (EfiCpuIoWidthUint32, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
}
UINT8
PciRead8 (
UINT8 Segment,
UINT8 Bus,
UINT8 DevFunc,
UINT8 Register
)
/*++
Routine Description:
Perform an one byte PCI config cycle read
Arguments:
Segment - PCI Segment ACPI _SEG
Bus - PCI Bus
DevFunc - PCI Device(7:3) and Func(2:0)
Register - PCI config space register
Returns:
Data read from PCI config space
--*/
{
EFI_STATUS Status;
UINT32 PciAddress;
UINT32 PciAddress1;
UINT8 Data;
PciAddress = GetPciAddress (Segment, Bus, DevFunc, Register);
//
// Set bit 31 for PCI config access
//
PciAddress1 = PciAddress;
PciAddress = ((PciAddress & 0xFFFFFFFC) | (0x80000000));
Status = EfiIoWrite (EfiCpuIoWidthUint32, PCI_CONFIG_INDEX_PORT, 1, &PciAddress);
if (EFI_ERROR (Status)) {
return 0;
}
EfiIoRead (EfiCpuIoWidthUint8, (PCI_CONFIG_DATA_PORT + (PciAddress1 & 0x3)), 1, &Data);
return Data;
}
VOID
IoWrite8 (
IN UINT64 Address,
IN UINT8 Data
)
/*++
Routine Description:
Do a one byte IO write
Arguments:
Address - IO address to write
Data - Data to write to Address
Returns:
NONE
--*/
{
EfiIoWrite (EfiCpuIoWidthUint8, Address, 1, &Data);
}
