/**Function*************************************************************
Synopsis [Write the network into a BLIF file with the given name.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteBlifMv( Abc_Ntk_t * pNtk, char * FileName )
{
FILE * pFile;
Abc_Ntk_t * pNtkTemp;
int i;
assert( Abc_NtkIsNetlist(pNtk) );
assert( Abc_NtkHasBlifMv(pNtk) );
// start writing the file
pFile = fopen( FileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteBlifMv(): Cannot open the output file.\n" );
return;
}
fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
// write the master network
Io_NtkWriteBlifMv( pFile, pNtk );
// write the remaining networks
if ( pNtk->pDesign )
{
Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNtkTemp, i )
{
if ( pNtkTemp == pNtk )
continue;
fprintf( pFile, "\n\n" );
Io_NtkWriteBlifMv( pFile, pNtkTemp );
}
}
/**Function*************************************************************
Synopsis [Write the network into a BLIF file with the given name.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches, int fBb2Wb, int fSeq )
{
FILE * pFile;
Abc_Ntk_t * pNtkTemp;
int i;
assert( Abc_NtkIsNetlist(pNtk) );
// start writing the file
pFile = fopen( FileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteBlif(): Cannot open the output file.\n" );
return;
}
fprintf( pFile, "# Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
// write the master network
Io_NtkWrite( pFile, pNtk, fWriteLatches, fBb2Wb, fSeq );
// make sure there is no logic hierarchy
assert( Abc_NtkWhiteboxNum(pNtk) == 0 );
// write the hierarchy if present
if ( Abc_NtkBlackboxNum(pNtk) > 0 )
{
Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNtkTemp, i )
{
if ( pNtkTemp == pNtk )
continue;
fprintf( pFile, "\n\n" );
Io_NtkWrite( pFile, pNtkTemp, fWriteLatches, fBb2Wb, fSeq );
}
}
/**Function*************************************************************
Synopsis [Writes the logic network in the equation format.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteEqn( Abc_Ntk_t * pNtk, char * pFileName )
{
FILE * pFile;
assert( Abc_NtkIsAigNetlist(pNtk) );
if ( Abc_NtkLatchNum(pNtk) > 0 )
printf( "Warning: only combinational portion is being written.\n" );
// check that the names are fine for the EQN format
if ( !Io_NtkWriteEqnCheck(pNtk) )
return;
// start the output stream
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteEqn(): Cannot open the output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "# Equations for \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
// write the equations for the network
Io_NtkWriteEqnOne( pFile, pNtk );
fprintf( pFile, "\n" );
fclose( pFile );
}
/**Function*************************************************************
Synopsis [Writes the graph structure of AIG in GML.]
Description [Useful for graph visualization using tools such as yEd:
http://www.yworks.com/]
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteGml( Abc_Ntk_t * pNtk, char * pFileName )
{
FILE * pFile;
Abc_Obj_t * pObj, * pFanin;
int i, k;
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
// start the output stream
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteGml(): Cannot open the output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "# GML for \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
fprintf( pFile, "graph [\n" );
// output the POs
fprintf( pFile, "\n" );
Abc_NtkForEachPo( pNtk, pObj, i )
{
fprintf( pFile, " node [ id %5d label \"%s\"\n", pObj->Id, Abc_ObjName(pObj) );
fprintf( pFile, " graphics [ type \"triangle\" fill \"#00FFFF\" ]\n" ); // blue
fprintf( pFile, " ]\n" );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_GenSorter( char * pFileName, int nVars )
{
FILE * pFile;
int i, k, Counter, nDigits;
assert( nVars > 1 );
pFile = fopen( pFileName, "w" );
fprintf( pFile, "# %d-bit sorter generated by ABC on %s\n", nVars, Extra_TimeStamp() );
fprintf( pFile, ".model Sorter%02d\n", nVars );
fprintf( pFile, ".inputs" );
for ( i = 0; i < nVars; i++ )
fprintf( pFile, " x%02d", i );
fprintf( pFile, "\n" );
fprintf( pFile, ".outputs" );
for ( i = 0; i < nVars; i++ )
fprintf( pFile, " y%02d", i );
fprintf( pFile, "\n" );
Counter = 0;
nDigits = Extra_Base10Log( (nVars-2)*nVars );
if ( nVars == 2 )
fprintf( pFile, ".subckt Comp a=x00 b=x01 x=y00 y=y01\n" );
else
{
fprintf( pFile, ".subckt Layer0" );
for ( k = 0; k < nVars; k++ )
fprintf( pFile, " x%02d=x%02d", k, k );
for ( k = 0; k < nVars; k++ )
fprintf( pFile, " y%02d=%0*d", k, nDigits, Counter++ );
fprintf( pFile, "\n" );
Counter -= nVars;
for ( i = 1; i < nVars-2; i++ )
{
fprintf( pFile, ".subckt Layer%d", (i&1) );
for ( k = 0; k < nVars; k++ )
fprintf( pFile, " x%02d=%0*d", k, nDigits, Counter++ );
for ( k = 0; k < nVars; k++ )
fprintf( pFile, " y%02d=%0*d", k, nDigits, Counter++ );
fprintf( pFile, "\n" );
Counter -= nVars;
}
fprintf( pFile, ".subckt Layer%d", (i&1) );
for ( k = 0; k < nVars; k++ )
fprintf( pFile, " x%02d=%0*d", k, nDigits, Counter++ );
for ( k = 0; k < nVars; k++ )
fprintf( pFile, " y%02d=y%02d", k, k );
fprintf( pFile, "\n" );
}
fprintf( pFile, ".end\n" );
fprintf( pFile, "\n" );
Abc_WriteLayer( pFile, nVars, 0 );
Abc_WriteLayer( pFile, nVars, 1 );
Abc_WriteComp( pFile );
fclose( pFile );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_GenMesh( char * pFileName, int nVars )
{
FILE * pFile;
int i, k;
assert( nVars > 0 );
pFile = fopen( pFileName, "w" );
fprintf( pFile, "# %dx%d mesh generated by ABC on %s\n", nVars, nVars, Extra_TimeStamp() );
fprintf( pFile, ".model mesh%d\n", nVars );
for ( i = 0; i < nVars; i++ )
for ( k = 0; k < nVars; k++ )
{
fprintf( pFile, ".inputs" );
fprintf( pFile, " p%d%dx1", i, k );
fprintf( pFile, " p%d%dx2", i, k );
fprintf( pFile, " p%d%dy1", i, k );
fprintf( pFile, " p%d%dy2", i, k );
fprintf( pFile, "\n" );
}
fprintf( pFile, ".inputs" );
for ( i = 0; i < nVars; i++ )
fprintf( pFile, " v%02d v%02d", 2*i, 2*i+1 );
fprintf( pFile, "\n" );
fprintf( pFile, ".outputs" );
fprintf( pFile, " fx00" );
fprintf( pFile, "\n" );
for ( i = 0; i < nVars; i++ ) // horizontal
for ( k = 0; k < nVars; k++ ) // vertical
{
fprintf( pFile, ".subckt cell" );
fprintf( pFile, " px1=p%d%dx1", i, k );
fprintf( pFile, " px2=p%d%dx2", i, k );
fprintf( pFile, " py1=p%d%dy1", i, k );
fprintf( pFile, " py2=p%d%dy2", i, k );
if ( k == nVars - 1 )
fprintf( pFile, " x=v%02d", i );
else
fprintf( pFile, " x=fx%d%d", i, k+1 );
if ( i == nVars - 1 )
fprintf( pFile, " y=v%02d", nVars+k );
else
fprintf( pFile, " y=fy%d%d", i+1, k );
// outputs
fprintf( pFile, " fx=fx%d%d", i, k );
fprintf( pFile, " fy=fy%d%d", i, k );
fprintf( pFile, "\n" );
}
fprintf( pFile, ".end\n" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
Abc_WriteCell( pFile );
fclose( pFile );
}
void Cba_PrsWriteBlif( char * pFileName, Cba_Man_t * pDes )
{
FILE * pFile;
Cba_Ntk_t * pNtk;
int i;
pFile = fopen( pFileName, "wb" );
if ( pFile == NULL )
{
printf( "Cannot open output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "// Design \"%s\" written by ABC on %s\n\n", Cba_ManName(pDes), Extra_TimeStamp() );
Cba_ManForEachNtk( pDes, pNtk, i )
Cba_PrsWriteBlifNtk( pFile, pNtk );
fclose( pFile );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_GenAdder( char * pFileName, int nVars )
{
FILE * pFile;
int i;
assert( nVars > 0 );
pFile = fopen( pFileName, "w" );
fprintf( pFile, "# %d-bit ripple-carry adder generated by ABC on %s\n", nVars, Extra_TimeStamp() );
fprintf( pFile, ".model Adder%02d\n", nVars );
fprintf( pFile, ".inputs" );
for ( i = 0; i < nVars; i++ )
fprintf( pFile, " a%02d", i );
for ( i = 0; i < nVars; i++ )
fprintf( pFile, " b%02d", i );
fprintf( pFile, "\n" );
fprintf( pFile, ".outputs" );
for ( i = 0; i <= nVars; i++ )
fprintf( pFile, " y%02d", i );
fprintf( pFile, "\n" );
fprintf( pFile, ".names c\n" );
if ( nVars == 1 )
fprintf( pFile, ".subckt FA a=a00 b=b00 cin=c s=y00 cout=y01\n" );
else
{
fprintf( pFile, ".subckt FA a=a00 b=b00 cin=c s=y00 cout=%02d\n", 0 );
for ( i = 1; i < nVars-1; i++ )
fprintf( pFile, ".subckt FA a=a%02d b=b%02d cin=%02d s=y%02d cout=%02d\n", i, i, i-1, i, i );
fprintf( pFile, ".subckt FA a=a%02d b=b%02d cin=%02d s=y%02d cout=y%02d\n", i, i, i-1, i, i+1 );
}
fprintf( pFile, ".end\n" );
fprintf( pFile, "\n" );
Abc_WriteFullAdder( pFile );
fclose( pFile );
}
/**Function*************************************************************
Synopsis [Write verilog.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName )
{
Abc_Ntk_t * pNetlist;
FILE * pFile;
int i;
// can only write nodes represented using local AIGs
if ( !Abc_NtkIsAigNetlist(pNtk) && !Abc_NtkIsMappedNetlist(pNtk) )
{
printf( "Io_WriteVerilog(): Can produce Verilog for mapped or AIG netlists only.\n" );
return;
}
// start the output stream
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteVerilog(): Cannot open the output file \"%s\".\n", pFileName );
return;
}
// write the equations for the network
fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
fprintf( pFile, "\n" );
// write modules
if ( pNtk->pDesign )
{
// write the network first
Io_WriteVerilogInt( pFile, pNtk );
// write other things
Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNetlist, i )
{
assert( Abc_NtkIsNetlist(pNetlist) );
if ( pNetlist == pNtk )
continue;
fprintf( pFile, "\n" );
Io_WriteVerilogInt( pFile, pNetlist );
}
}
***********************************************************************/
void Mio_WriteLibrary( FILE * pFile, Mio_Library_t * pLib, int fPrintSops )
{
Mio_Gate_t * pGate;
Mio_Pin_t * pPin;
int i, GateLen = 0, NameLen = 0, FormLen = 0;
int fAllPins = Mio_CheckGates( pLib );
Mio_LibraryForEachGate( pLib, pGate )
{
GateLen = Abc_MaxInt( GateLen, strlen(pGate->pName) );
NameLen = Abc_MaxInt( NameLen, strlen(pGate->pOutName) );
FormLen = Abc_MaxInt( FormLen, strlen(pGate->pForm) );
Mio_GateForEachPin( pGate, pPin )
NameLen = Abc_MaxInt( NameLen, strlen(pPin->pName) );
}
fprintf( pFile, "# The genlib library \"%s\" written by ABC on %s\n\n", pLib->pName, Extra_TimeStamp() );
for ( i = 0; i < pLib->nGates; i++ )
Mio_WriteGate( pFile, pLib->ppGates0[i], GateLen, NameLen, FormLen, fPrintSops, fAllPins );
}
/**Function*************************************************************
Synopsis [Compares the max delay of two gates.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cba_PtrDumpVerilog( char * pFileName, Vec_Ptr_t * vDes )
{
FILE * pFile;
Vec_Ptr_t * vNtk; int i;
pFile = fopen( pFileName, "wb" );
if ( pFile == NULL )
{
printf( "Cannot open output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "// Design \"%s\" written via Ptr in ABC on %s\n\n", (char *)Vec_PtrEntry(vDes, 0), Extra_TimeStamp() );
Vec_PtrForEachEntryStart( Vec_Ptr_t *, vDes, vNtk, i, 1 )
Cba_PtrDumpModuleVerilog( pFile, vNtk );
fclose( pFile );
}
/**Function*************************************************************
Synopsis [Generates structure of L K-LUTs implementing an N-var function.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_GenFpga( char * pFileName, int nLutSize, int nLuts, int nVars )
{
FILE * pFile;
int nVarsLut = (1 << nLutSize); // the number of LUT variables
int nVarsLog = Extra_Base2Log( nVars + nLuts - 1 ); // the number of encoding vars
int nVarsDeg = (1 << nVarsLog); // the number of LUT variables (total)
int nParsLut = nLuts * (1 << nLutSize); // the number of LUT params
int nParsVar = nLuts * nLutSize * nVarsLog; // the number of var params
int i, j, k;
assert( nVars > 0 );
pFile = fopen( pFileName, "w" );
fprintf( pFile, "# Structure with %d %d-LUTs for %d-var function generated by ABC on %s\n", nLuts, nLutSize, nVars, Extra_TimeStamp() );
fprintf( pFile, ".model struct%dx%d_%d\n", nLuts, nLutSize, nVars );
fprintf( pFile, ".inputs" );
for ( i = 0; i < nParsLut; i++ )
fprintf( pFile, " pl%02d", i );
fprintf( pFile, "\n" );
fprintf( pFile, ".inputs" );
for ( i = 0; i < nParsVar; i++ )
fprintf( pFile, " pv%02d", i );
fprintf( pFile, "\n" );
fprintf( pFile, ".inputs" );
for ( i = 0; i < nVars; i++ )
fprintf( pFile, " v%02d", i );
fprintf( pFile, "\n" );
fprintf( pFile, ".outputs" );
fprintf( pFile, " v%02d", nVars + nLuts - 1 );
fprintf( pFile, "\n" );
fprintf( pFile, ".names Gnd\n" );
fprintf( pFile, " 0\n" );
// generate LUTs
for ( i = 0; i < nLuts; i++ )
{
fprintf( pFile, ".subckt lut%d", nLutSize );
// generate config parameters
for ( k = 0; k < nVarsLut; k++ )
fprintf( pFile, " p%02d=pl%02d", k, i * nVarsLut + k );
// generate the inputs
for ( k = 0; k < nLutSize; k++ )
fprintf( pFile, " i%d=s%02d", k, i * nLutSize + k );
// generate the output
fprintf( pFile, " o=v%02d", nVars + i );
fprintf( pFile, "\n" );
}
// generate LUT inputs
for ( i = 0; i < nLuts; i++ )
{
for ( j = 0; j < nLutSize; j++ )
{
fprintf( pFile, ".subckt lut%d", nVarsLog );
// generate config parameters
for ( k = 0; k < nVarsDeg; k++ )
{
if ( k < nVars + nLuts - 1 && k < nVars + i )
fprintf( pFile, " p%02d=v%02d", k, k );
else
fprintf( pFile, " p%02d=Gnd", k );
}
// generate the inputs
for ( k = 0; k < nVarsLog; k++ )
fprintf( pFile, " i%d=pv%02d", k, (i * nLutSize + j) * nVarsLog + k );
// generate the output
fprintf( pFile, " o=s%02d", i * nLutSize + j );
fprintf( pFile, "\n" );
}
}
fprintf( pFile, ".end\n" );
fprintf( pFile, "\n" );
// generate LUTs
Abc_WriteKLut( pFile, nLutSize );
if ( nVarsLog != nLutSize )
Abc_WriteKLut( pFile, nVarsLog );
fclose( pFile );
}
/**Function*************************************************************
Synopsis [Writes the graph structure of network for DOT.]
Description [Useful for graph visualization using tools such as GraphViz:
http://www.graphviz.org/]
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse )
{
FILE * pFile;
Abc_Obj_t * pNode, * pFanin;
char * pSopString;
int LevelMin, LevelMax, fHasCos, Level, i, k, fHasBdds, fCompl;
int Limit = 300;
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( vNodes->nSize < 1 )
{
printf( "The set has no nodes. DOT file is not written.\n" );
return;
}
if ( vNodes->nSize > Limit )
{
printf( "The set has more than %d nodes. DOT file is not written.\n", Limit );
return;
}
// start the stream
if ( (pFile = fopen( pFileName, "w" )) == NULL )
{
fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", pFileName );
return;
}
// transform logic functions from BDD to SOP
if ( fHasBdds = Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, 0) )
{
printf( "Io_WriteDotNtk(): Converting to SOPs has failed.\n" );
return;
}
}
// mark the nodes from the set
Vec_PtrForEachEntry( vNodes, pNode, i )
pNode->fMarkC = 1;
if ( vNodesShow )
Vec_PtrForEachEntry( vNodesShow, pNode, i )
pNode->fMarkB = 1;
// get the levels of nodes
LevelMax = Abc_NtkLevel( pNtk );
if ( fUseReverse )
{
LevelMin = Abc_NtkLevelReverse( pNtk );
assert( LevelMax == LevelMin );
Vec_PtrForEachEntry( vNodes, pNode, i )
if ( Abc_ObjIsNode(pNode) )
pNode->Level = LevelMax - pNode->Level + 1;
}
// find the largest and the smallest levels
LevelMin = 10000;
LevelMax = -1;
fHasCos = 0;
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCo(pNode) )
{
fHasCos = 1;
continue;
}
if ( LevelMin > (int)pNode->Level )
LevelMin = pNode->Level;
if ( LevelMax < (int)pNode->Level )
LevelMax = pNode->Level;
}
// set the level of the CO nodes
if ( fHasCos )
{
LevelMax++;
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCo(pNode) )
pNode->Level = LevelMax;
}
}
// write the DOT header
fprintf( pFile, "# %s\n", "Network structure generated by ABC" );
fprintf( pFile, "\n" );
fprintf( pFile, "digraph network {\n" );
fprintf( pFile, "size = \"7.5,10\";\n" );
// fprintf( pFile, "size = \"10,8.5\";\n" );
// fprintf( pFile, "size = \"14,11\";\n" );
// fprintf( pFile, "page = \"8,11\";\n" );
// fprintf( pFile, "ranksep = 0.5;\n" );
// fprintf( pFile, "nodesep = 0.5;\n" );
fprintf( pFile, "center = true;\n" );
// fprintf( pFile, "orientation = landscape;\n" );
// fprintf( pFile, "edge [fontsize = 10];\n" );
// fprintf( pFile, "edge [dir = none];\n" );
fprintf( pFile, "edge [dir = back];\n" );
fprintf( pFile, "\n" );
// labels on the left of the picture
fprintf( pFile, "{\n" );
fprintf( pFile, " node [shape = plaintext];\n" );
fprintf( pFile, " edge [style = invis];\n" );
fprintf( pFile, " LevelTitle1 [label=\"\"];\n" );
fprintf( pFile, " LevelTitle2 [label=\"\"];\n" );
// generate node names with labels
for ( Level = LevelMax; Level >= LevelMin; Level-- )
{
// the visible node name
fprintf( pFile, " Level%d", Level );
fprintf( pFile, " [label = " );
// label name
fprintf( pFile, "\"" );
fprintf( pFile, "\"" );
fprintf( pFile, "];\n" );
}
// genetate the sequence of visible/invisible nodes to mark levels
fprintf( pFile, " LevelTitle1 -> LevelTitle2 ->" );
for ( Level = LevelMax; Level >= LevelMin; Level-- )
{
// the visible node name
fprintf( pFile, " Level%d", Level );
// the connector
if ( Level != LevelMin )
fprintf( pFile, " ->" );
else
fprintf( pFile, ";" );
}
fprintf( pFile, "\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate title box on top
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
fprintf( pFile, " LevelTitle1;\n" );
fprintf( pFile, " title1 [shape=plaintext,\n" );
fprintf( pFile, " fontsize=20,\n" );
fprintf( pFile, " fontname = \"Times-Roman\",\n" );
fprintf( pFile, " label=\"" );
fprintf( pFile, "%s", "Network structure visualized by ABC" );
fprintf( pFile, "\\n" );
fprintf( pFile, "Benchmark \\\"%s\\\". ", pNtk->pName );
fprintf( pFile, "Time was %s. ", Extra_TimeStamp() );
fprintf( pFile, "\"\n" );
fprintf( pFile, " ];\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate statistics box
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
fprintf( pFile, " LevelTitle2;\n" );
fprintf( pFile, " title2 [shape=plaintext,\n" );
fprintf( pFile, " fontsize=18,\n" );
fprintf( pFile, " fontname = \"Times-Roman\",\n" );
fprintf( pFile, " label=\"" );
if ( Abc_NtkObjNum(pNtk) == Vec_PtrSize(vNodes) )
fprintf( pFile, "The network contains %d logic nodes and %d latches.", Abc_NtkNodeNum(pNtk), Abc_NtkLatchNum(pNtk) );
else
fprintf( pFile, "The set contains %d logic nodes and spans %d levels.", Abc_NtkCountLogicNodes(vNodes), LevelMax - LevelMin + 1 );
fprintf( pFile, "\\n" );
fprintf( pFile, "\"\n" );
fprintf( pFile, " ];\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate the POs
if ( fHasCos )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", LevelMax );
// generate the PO nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( !Abc_ObjIsCo(pNode) )
continue;
fprintf( pFile, " Node%d [label = \"%s%s\"",
pNode->Id,
(Abc_ObjIsBi(pNode)? Abc_ObjName(Abc_ObjFanout0(pNode)):Abc_ObjName(pNode)),
(Abc_ObjIsBi(pNode)? "_in":"") );
fprintf( pFile, ", shape = %s", (Abc_ObjIsBi(pNode)? "box":"invtriangle") );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
// generate nodes of each rank
for ( Level = LevelMax - fHasCos; Level >= LevelMin && Level > 0; Level-- )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", Level );
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( (int)pNode->Level != Level )
continue;
if ( Abc_ObjFaninNum(pNode) == 0 )
continue;
// fprintf( pFile, " Node%d [label = \"%d\"", pNode->Id, pNode->Id );
if ( Abc_NtkIsStrash(pNtk) )
pSopString = "";
else if ( Abc_NtkHasMapping(pNtk) && fGateNames )
pSopString = Mio_GateReadName(pNode->pData);
else if ( Abc_NtkHasMapping(pNtk) )
pSopString = Abc_NtkPrintSop(Mio_GateReadSop(pNode->pData));
else
pSopString = Abc_NtkPrintSop(pNode->pData);
fprintf( pFile, " Node%d [label = \"%d\\n%s\"", pNode->Id, pNode->Id, pSopString );
fprintf( pFile, ", shape = ellipse" );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
// generate the PI nodes if any
if ( LevelMin == 0 )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", LevelMin );
// generate the PO nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( !Abc_ObjIsCi(pNode) )
{
// check if the costant node is present
if ( Abc_ObjFaninNum(pNode) == 0 && Abc_ObjFanoutNum(pNode) > 0 )
{
fprintf( pFile, " Node%d [label = \"Const%d\"", pNode->Id, Abc_NtkIsStrash(pNode->pNtk) || Abc_NodeIsConst1(pNode) );
fprintf( pFile, ", shape = ellipse" );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
continue;
}
fprintf( pFile, " Node%d [label = \"%s\"",
pNode->Id,
(Abc_ObjIsBo(pNode)? Abc_ObjName(Abc_ObjFanin0(pNode)):Abc_ObjName(pNode)) );
fprintf( pFile, ", shape = %s", (Abc_ObjIsBo(pNode)? "box":"triangle") );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}