Exemplo n.º 1
0
static void i8xx_fbc_enable(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
	struct drm_framebuffer *fb = crtc->base.primary->fb;
	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
	int cfb_pitch;
	int i;
	u32 fbc_ctl;

	dev_priv->fbc.enabled = true;

	/* Note: fbc.threshold == 1 for i8xx */
	cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE;
	if (fb->pitches[0] < cfb_pitch)
		cfb_pitch = fb->pitches[0];

	/* FBC_CTL wants 32B or 64B units */
	if (IS_GEN2(dev_priv))
		cfb_pitch = (cfb_pitch / 32) - 1;
	else
		cfb_pitch = (cfb_pitch / 64) - 1;

	/* Clear old tags */
	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
		I915_WRITE(FBC_TAG(i), 0);

	if (IS_GEN4(dev_priv)) {
		u32 fbc_ctl2;

		/* Set it up... */
		fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
		fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane);
		I915_WRITE(FBC_CONTROL2, fbc_ctl2);
		I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc));
	}

	/* enable it... */
	fbc_ctl = I915_READ(FBC_CONTROL);
	fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
	fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
	if (IS_I945GM(dev_priv))
		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
	fbc_ctl |= obj->fence_reg;
	I915_WRITE(FBC_CONTROL, fbc_ctl);

	DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
		      cfb_pitch, crtc->base.y, plane_name(crtc->plane));
}
static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
{
    struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
    int cfb_pitch;
    int i;
    u32 fbc_ctl;

    dev_priv->fbc.active = true;

    /* Note: fbc.threshold == 1 for i8xx */
    cfb_pitch = params->cfb_size / FBC_LL_SIZE;
    if (params->fb.stride < cfb_pitch)
        cfb_pitch = params->fb.stride;

    /* FBC_CTL wants 32B or 64B units */
    if (IS_GEN2(dev_priv))
        cfb_pitch = (cfb_pitch / 32) - 1;
    else
        cfb_pitch = (cfb_pitch / 64) - 1;

    /* Clear old tags */
    for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
        I915_WRITE(FBC_TAG(i), 0);

    if (IS_GEN4(dev_priv)) {
        u32 fbc_ctl2;

        /* Set it up... */
        fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
        fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
        I915_WRITE(FBC_CONTROL2, fbc_ctl2);
        I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
    }

    /* enable it... */
    fbc_ctl = I915_READ(FBC_CONTROL);
    fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
    fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
    if (IS_I945GM(dev_priv))
        fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
    fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
    fbc_ctl |= params->fb.fence_reg;
    I915_WRITE(FBC_CONTROL, fbc_ctl);
}