static int __init graphicsmaster_init(void)
{
int ret;
if (!machine_is_graphicsmaster())
return -ENODEV;
/*
* Ensure that the memory bus request/grant signals are setup,
* and the grant is held in its inactive state
*/
sa1110_mb_disable();
/*
* Probe for SA1111.
*/
ret = sa1111_probe(ADS_SA1111_BASE);
if (ret < 0)
return ret;
/*
* We found it. Wake the chip up.
*/
sa1111_wake();
/*
* The SDRAM configuration of the SA1110 and the SA1111 must
* match. This is very important to ensure that SA1111 accesses
* don't corrupt the SDRAM. Note that this ungates the SA1111's
* MBGNT signal, so we must have called sa1110_mb_disable()
* beforehand.
*/
sa1111_configure_smc(1,
FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
/*
* Enable PWM control for LCD
*/
SKPCR |= SKPCR_PWMCLKEN;
SKPWM0 = 0x7F; // VEE
SKPEN0 = 1;
SKPWM1 = 0x01; // Backlight
SKPEN1 = 1;
/*
* We only need to turn on DCLK whenever we want to use the
* DMA. It can otherwise be held firmly in the off position.
*/
SKPCR |= SKPCR_DCLKEN;
/*
* Enable the SA1110 memory bus request and grant signals.
*/
sa1110_mb_enable();
sa1111_init_irq(IRQ_BOARD_START);
return 0;
}
/* According to the "Intel StrongARM SA-1111 Microprocessor Companion
* Chip Specification Update" (June 2000), erratum #7, there is a
* significant bug in Serial Audio Controller DMA. If the SAC is
* accessing a region of memory above 1MB relative to the bank base,
* it is important that address bit 10 _NOT_ be asserted. Depending
* on the configuration of the RAM, bit 10 may correspond to one
* of several different (processor-relative) address bits.
*
* This routine only identifies whether or not a given DMA address
* is susceptible to the bug.
*/
int sa1111_check_dma_bug(dma_addr_t addr){
unsigned int physaddr=SA1111_DMA_ADDR((unsigned int)addr);
/* Section 4.6 of the "Intel StrongARM SA-1111 Development Module
* User's Guide" mentions that jumpers R51 and R52 control the
* target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
* SDRAM bank 1 on Neponset). The default configuration selects
* Assabet, so any address in bank 1 is necessarily invalid.
*/
if((machine_is_assabet() || machine_is_pfs168() ||
machine_is_graphicsmaster() || machine_is_adsagc()) && addr >= 0xc8000000)
return -1;
/* The bug only applies to buffers located more than one megabyte
* above the start of the target bank:
*/
if(physaddr<(1<<20))
return 0;
switch(FExtr(SBI_SMCR, SMCR_DRAC)){
case 01: /* 10 row + bank address bits, A<20> must not be set */
if(physaddr & (1<<20))
return -1;
break;
case 02: /* 11 row + bank address bits, A<23> must not be set */
if(physaddr & (1<<23))
return -1;
break;
case 03: /* 12 row + bank address bits, A<24> must not be set */
if(physaddr & (1<<24))
return -1;
break;
case 04: /* 13 row + bank address bits, A<25> must not be set */
if(physaddr & (1<<25))
return -1;
break;
case 05: /* 14 row + bank address bits, A<20> must not be set */
if(physaddr & (1<<20))
return -1;
break;
case 06: /* 15 row + bank address bits, A<20> must not be set */
if(physaddr & (1<<20))
return -1;
break;
default:
printk(KERN_ERR "%s(): invalid SMCR DRAC value 0%lo\n",
__FUNCTION__, FExtr(SBI_SMCR, SMCR_DRAC));
return -1;
}
return 0;
}
/*
* Resume SA1111 when system wakes up
*/
void adsbitsyplus_sa1111_wake(unsigned long pa_dwr)
{
// Turn ON SA1111
GPCR |= GPIO_GPIO26;
mdelay(1);
GPSR |= GPIO_GPIO26;
GAFR |= GPIO_32_768kHz;
GPDR |= GPIO_32_768kHz;
TUCR = TUCR_3_6864MHz;
SBI_SKCR = SKCR_PLL_BYPASS | SKCR_RDYEN | SKCR_OE_EN;
udelay(100);
SBI_SKCR = SKCR_PLL_BYPASS | SKCR_RCLKEN | SKCR_RDYEN | SKCR_OE_EN;
GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
GPDR |= GPIO_MBGNT;
GPDR &= ~GPIO_MBREQ;
TUCR |= TUCR_MR;
sa1111_configure_smc(1,
FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
SKPCR |= SKPCR_DCLKEN;
// Reset PCMCIA
PCCR = 0xFF;
mdelay(100);
PA_DDR = 0x00;
// PA_DWR = GPIO_GPIO0 | GPIO_GPIO1 | GPIO_GPIO2 | GPIO_GPIO3;
// PA_DWR = GPIO_GPIO0 | GPIO_GPIO2 | GPIO_GPIO3;
PA_DWR = pa_dwr;
PCCR = ~(PCCR_S0_RST | PCCR_S1_RST);
#ifdef CONFIG_USB_OHCI_SA1111
// Turn ON clock
SKPCR |= SKPCR_UCLKEN;
udelay(100);
// force a RESET
USB_RESET = 0x01;
USB_RESET |= 0x02;
udelay(100);
// Set Power Sense and Control Line
USB_RESET = 0;
USB_RESET = USB_RESET_PWRSENSELOW;
USB_STATUS = 0;
udelay(10);
#endif
}
static int __init adsbitsy_init(void)
{
int ret;
if (!machine_is_adsbitsy())
return -ENODEV;
/*
* Ensure that the memory bus request/grant signals are setup,
* and the grant is held in its inactive state
*/
sa1110_mb_disable();
/* Bitsy uses GPIO pins for SPI interface to AVR
* Bitsy Plus uses the standard pins instead.
* it also needs to reset the AVR when booting
*/
PPAR |= PPAR_SSPGPIO;
/*
* Reset SA1111
*/
GPCR |= GPIO_GPIO26;
udelay(1000);
GPSR |= GPIO_GPIO26;
#ifndef CONFIG_LEDS_TIMER
// Set Serial port 1 RTS and DTR Low during sleep
PGSR |= GPIO_GPIO15 | GPIO_GPIO20;
#else
// only RTS (because DTR is also the LED
// which should be off during sleep);
PGSR |= GPIO_GPIO15;
#endif
// Set Serial port 3RTS Low during sleep
PGSR |= GPIO_GPIO19;
/*
* Probe for SA1111.
*/
ret = sa1111_probe(ADSBITSY_SA1111_BASE);
if (ret < 0)
return ret;
/*
* We found it. Wake the chip up.
*/
sa1111_wake();
/*
* The SDRAM configuration of the SA1110 and the SA1111 must
* match. This is very important to ensure that SA1111 accesses
* don't corrupt the SDRAM. Note that this ungates the SA1111's
* MBGNT signal, so we must have called sa1110_mb_disable()
* beforehand.
*/
sa1111_configure_smc(1,
FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
/*
* We only need to turn on DCLK whenever we want to use the
* DMA. It can otherwise be held firmly in the off position.
*/
SKPCR |= SKPCR_DCLKEN;
/*
* Enable the SA1110 memory bus request and grant signals.
*/
sa1110_mb_enable();
set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_RISING_EDGE);
sa1111_init_irq(IRQ_GPIO0);
return 0;
}
static int __init graphicsmaster_init(void)
{
int ret;
if (!machine_is_graphicsmaster())
return -ENODEV;
/*
* Ensure that the memory bus request/grant signals are setup,
* and the grant is held in its inactive state
*/
sa1110_mb_disable();
/* GraphicsMaster uses GPIO pins for SPI interface to AVR
*/
/* use the alternate SSP pins */
PPAR |= PPAR_SSPGPIO;
// Set RTS low during sleep
PGSR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19;
/*
* Probe for SA1111.
*/
ret = sa1111_probe(ADS_SA1111_BASE);
if (ret < 0)
return ret;
/*
* We found it. Wake the chip up.
*/
sa1111_wake();
/*
* The SDRAM configuration of the SA1110 and the SA1111 must
* match. This is very important to ensure that SA1111 accesses
* don't corrupt the SDRAM. Note that this ungates the SA1111's
* MBGNT signal, so we must have called sa1110_mb_disable()
* beforehand.
*/
sa1111_configure_smc(1,
FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
/*
* Enable PWM control for LCD
*/
SKPCR |= SKPCR_PWMCLKEN;
SACR1 &= ~SACR1_L3EN;
ADS_DCR |= DCR_BACKLITE_ON;
SKPWM0 = 0x01; // Backlight
SKPEN0 = 1;
SKPWM1 = 0x7F; // VEE
SKPEN1 = 1;
/*
* We only need to turn on DCLK whenever we want to use the
* DMA. It can otherwise be held firmly in the off position.
*/
SKPCR |= SKPCR_DCLKEN;
/*
* Enable the SA1110 memory bus request and grant signals.
*/
sa1110_mb_enable();
sa1111_init_irq(IRQ_GRAPHICSMASTER_SA1111);
return 0;
}
static int __init system3_init(void)
{
int ret = 0;
DPRINTK( "%s\n", "START" );
if ( !machine_is_pt_system3() ) {
ret = -EINVAL;
goto DONE;
}
/* init control register */
PT_CTRL0 = PT_CTRL0_INIT;
PT_CTRL1 = 0x02;
PT_CTRL2 = 0x00;
DPRINTK( "CTRL[0]=0x%02x\n", PT_CTRL0 );
DPRINTK( "CTRL[1]=0x%02x\n", PT_CTRL1 );
DPRINTK( "CTRL[2]=0x%02x\n", PT_CTRL2 );
/*
* Ensure that the memory bus request/grant signals are setup,
* and the grant is held in its inactive state.
*/
sa1110_mb_disable();
/*
* Probe for a SA1111.
*/
ret = sa1111_probe(PT_SA1111_BASE);
if (ret < 0) {
printk( KERN_WARNING"PT Digital Board: no SA1111 found!\n" );
goto DONE;
}
/*
* We found it. Wake the chip up.
*/
sa1111_wake();
/*
* The SDRAM configuration of the SA1110 and the SA1111 must
* match. This is very important to ensure that SA1111 accesses
* don't corrupt the SDRAM. Note that this ungates the SA1111's
* MBGNT signal, so we must have called sa1110_mb_disable()
* beforehand.
*/
sa1111_configure_smc(1,
FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
/*
* We only need to turn on DCLK whenever we want to use the
* DMA. It can otherwise be held firmly in the off position.
*/
SKPCR |= SKPCR_DCLKEN;
/*
* Enable the SA1110 memory bus request and grant signals.
*/
sa1110_mb_enable();
system3_init_irq();
#if defined( CONFIG_CPU_FREQ )
ret = cpufreq_register_notifier(&system3_clkchg_block);
if ( ret != 0 ) {
printk( KERN_WARNING"PT Digital Board: could not register clock scale callback\n" );
goto DONE;
}
#endif
ret = 0;
DONE:
DPRINTK( "ret=%d\n", ret );
return ret;
}
static int __init neponset_init(void)
{
int ret;
/*
* The Neponset is only present on the Assabet machine type.
*/
if (!machine_is_assabet())
return -ENODEV;
/*
* Ensure that the memory bus request/grant signals are setup,
* and the grant is held in its inactive state, whether or not
* we actually have a Neponset attached.
*/
sa1110_mb_disable();
if (!machine_has_neponset()) {
printk(KERN_DEBUG "Neponset expansion board not present\n");
return -ENODEV;
}
if (WHOAMI != 0x11) {
printk(KERN_WARNING "Neponset board detected, but "
"wrong ID: %02x\n", WHOAMI);
return -ENODEV;
}
/*
* Disable GPIO 0/1 drivers so the buttons work on the module.
*/
NCR_0 |= NCR_GP01_OFF;
/*
* Neponset has SA1111 connected to CS4. We know that after
* reset the chip will be configured for variable latency IO.
*/
/* FIXME: setup MSC2 */
/*
* Probe for a SA1111.
*/
ret = sa1111_probe(NEPONSET_SA1111_BASE);
if (ret < 0)
return ret;
/*
* We found it. Wake the chip up.
*/
sa1111_wake();
/*
* The SDRAM configuration of the SA1110 and the SA1111 must
* match. This is very important to ensure that SA1111 accesses
* don't corrupt the SDRAM. Note that this ungates the SA1111's
* MBGNT signal, so we must have called sa1110_mb_disable()
* beforehand.
*/
sa1111_configure_smc(1,
FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
/*
* We only need to turn on DCLK whenever we want to use the
* DMA. It can otherwise be held firmly in the off position.
*/
SKPCR |= SKPCR_DCLKEN;
/*
* Enable the SA1110 memory bus request and grant signals.
*/
sa1110_mb_enable();
neponset_init_irq();
return 0;
}
