/**********************************************************************
* Chain a task by setting the calling task in a SUSPENDED state and
* the called taks in the READY state.
* Call the scheduler to jump the chained task.
*
* @param TaskID IN ID of the next task to chain
* @return Status E_OK if ID is not correct
* In fact the function never return
**********************************************************************/
StatusType ChainTask (TaskType TaskID)
{
ptrTCB thisTCB;
unsigned int * ptrRAM;
thisTCB = GetCurrentTCB();
thisTCB->State = SUSPENDED;
thisTCB = GetSpecificTCB(TaskID);
if (thisTCB == NULL)
return (E_OS_ID);
thisTCB->State = READY;
ptrRAM = thisTCB->StackAddress;
if (ptrRAM != NULL)
{
*ptrRAM++ = (unsigned int)(thisTCB->StartAddress);
*ptrRAM = 0;
thisTCB->Stack_register = SREG(thisTCB->StackAddress);
thisTCB->Frame_register = FREG(thisTCB->StackAddress);
}
DisableAllInterrupts();
kernelState |= KERNEL;
kernelState &= ~USER;
EnableAllInterrupts();
TaskLauncher();
return (E_OK);
}
/**********************************************************************
* Allow a task to terminate itself. Cannot terminate another task.
* To prepare a new activation of the task, we need first to store in
* stack the start adress of the task
*
* @param dest OUT Destination buffer
* @param src IN The byte to copy
* @return Status E_OK if ID is not correct
* In fact the function never return
**********************************************************************/
StatusType TerminateTask (void)
{
ptrTCB thisTCB;
unsigned int * ptrRAM;
thisTCB = GetCurrentTCB();
if (thisTCB->State & 0xF0)
thisTCB->State -= 0x10;
else
thisTCB->State = SUSPENDED;
ptrRAM = thisTCB->StackAddress;
if (ptrRAM != NULL)
{
*ptrRAM++ = (unsigned int)(thisTCB->StartAddress);
*ptrRAM = 0;
thisTCB->Stack_register = SREG(thisTCB->StackAddress);
thisTCB->Frame_register = FREG(thisTCB->StackAddress);
}
DisableAllInterrupts();
kernelState |= KERNEL;
kernelState &= ~USER;
EnableAllInterrupts();
TaskLauncher();
return (E_OK);
}
static mlib_status
mlib_s_SignalIFFTW_S16_S16C_0_4(
mlib_s16 *dstr,
const mlib_s16 *srcc,
const mlib_s16 *window,
mlib_s32 order)
{
__m128i dsrc, dsrc0, dsrc1, dsrc2, dsrc3, dst, dst1;
__m128i dsrc4, dsrc5, dsrc6, dsrc7, dst2, dst3;
__m128i dwin, dwin1, dwin2, dwin3;
__m128i fdst0;
__m128i fdst1;
__m128i fdst2;
mlib_s32 fonebytwo = 1;
DEF_ADDER(fonebytwo);
mlib_s32 foneby8 = 3;
DEF_ADDER(foneby8);
__m128i fsinpion4 = _mm_set1_epi32(0x5A825A82);
mlib_s32 gsr_shift;
switch (order) {
case 0:
dstr[0] = (srcc[0] * window[0]) >> 15;
break;
case 1:
gsr_shift = 1;
VIS_LDF_DBL(dwin, window);
VIS_LDD(dsrc, srcc);
MUL32_WIN(dsrc0, dsrc1, dwin, dsrc);
fdst0 =
SSE2_fpackfix_r(
FREG(add, hi, dsrc0, hi, dsrc1, sub, hi, dsrc0, hi, dsrc1));
VIS_STF(dstr, fdst0);
break;
case 2:
gsr_shift = 1;
VIS_LDD(dwin, window);
dwin = SSE2_fmul8x16(fonebytwo, dwin);
DBL_WIND(dwin, dwin1);
VIS_LDD_2(dsrc, dsrc3, srcc);
MUL32_WIN(dsrc0, dsrc1, dwin, dsrc);
MUL32_WIN(dsrc2, dsrc3, dwin1, dsrc3);
BUTT(dsrc, dsrc0, dsrc0, dsrc2);
BUTT(dst, dsrc1, dsrc1, dsrc3);
dst =
SSE2_fpackfix_pair_r(FREG(add, hi, dsrc, hi, dst, sub, hi,
dsrc0, lo, dsrc1), FREG(sub, hi, dsrc, hi, dst, add, hi,
dsrc0, lo, dsrc1));
VIS_STD(dstr, dst);
break;
case 3:
gsr_shift = 1;
VIS_LDD_2(dwin, dwin2, window);
dwin = SSE2_fmul8x16(foneby8, dwin);
dwin2 = SSE2_fmul8x16(foneby8, dwin2);
DBL_WIND(dwin, dwin1);
DBL_WIND(dwin2, dwin3);
VIS_LDD_4(dsrc1, dsrc3, dsrc5, dsrc7, srcc);
MUL32_WIN(dsrc0, dsrc1, dwin, dsrc1);
MUL32_WIN(dsrc2, dsrc3, dwin1, dsrc3);
MUL32_WIN(dsrc4, dsrc5, dwin2, dsrc5);
MUL32_WIN(dsrc6, dsrc7, dwin3, dsrc7);
BUTT(dst, dst1, dsrc0, dsrc4);
BUTT(dst2, dst3, dsrc2, dsrc6);
BUTT(dsrc4, dsrc5, dsrc1, dsrc5);
BUTT(dsrc6, dsrc7, dsrc3, dsrc7);
BUTT(dsrc0, dsrc2, dst, dst2);
BUTT_AS_HL(fdst1, fdst2, hi, dst1, lo, dst3);
BUTT(dst, dst2, dsrc4, dsrc6);
BUTT_FREG(dst3, dst1, hi, dsrc5, lo, dsrc7, lo, dsrc5, hi,
dsrc7);
fdst0 =
SSE2_fpackfix(FREG(sub, hi, dst1, lo, dst1, add, hi, dst3,
lo, dst3));
dsrc5 = MUL32F(fsinpion4, fdst0);
gsr_shift = 3;
dsrc4 =
SSE2_fpackfix_pair_r(FREG(add, hi, dsrc0, hi, dst, add, 00,
fdst2, hi, dsrc5), FREG(sub, hi, dsrc2, lo, dst2, sub, 00,
fdst1, lo, dsrc5));
dsrc5 =
SSE2_fpackfix_pair_r(FREG(sub, hi, dsrc0, hi, dst, sub, 00,
fdst2, hi, dsrc5), FREG(add, hi, dsrc2, lo, dst2, add, 00,
fdst1, lo, dsrc5));
VIS_STD_2(dstr, dsrc4, dsrc5);
break;
case 4: {
__m128i reim0, reim1, reim2, reim3, reim4, reim5, reim6,
reim7, tmp;
DCL_COMMON;
DCL_OUTVARR;
DCL_WINDOW;
PREP_OUTR;
LOAD_WINDOW;
LOAD_REIM;
MUL_RWIN;
MUL_IWIN;
PROC_FIRST_INV;
TRANSPOSE4X4_REV_NEW(ar, br, cr, dr, ar, br, cr, dr);
TRANSPOSE4X4_REV_NEW(ai, bi, ci, di, ai, bi, ci, di);
LOAD_ROT;
PROC_LAST_INV;
PROC_LAST_END_R;
STORE_RE;
}
break;
default:
return (MLIB_FAILURE);
}
return (MLIB_SUCCESS);
}
static mlib_status
mlib_s_SignalIFFTW_S16_S16_0_4(
mlib_s16 *dstr,
mlib_s16 *dsti,
const mlib_s16 *srcr,
const mlib_s16 *srci,
const mlib_s16 *window,
mlib_s32 order)
{
__m128i dsrc, dsrc0, dsrc1, dsrc2, dsrc3, dst, dst1;
__m128i dsrc4, dsrc5, dsrc6, dsrc7, dst2, dst3, dwin, dwin1;
__m128i fdst0;
__m128i fdst1;
mlib_s32 fonebytwo = 1;
DEF_ADDER(fonebytwo);
mlib_s32 foneby8 = 3;
DEF_ADDER(foneby8);
__m128i fsinpion4 = _mm_set1_epi32(0x5A825A82);
mlib_s32 gsr_shift;
switch (order) {
case 0:
dstr[0] = (srcr[0] * window[0]) >> 15;
dsti[0] = (srci[0] * window[0]) >> 15;
break;
case 1:
gsr_shift = 1;
VIS_LDF(dwin, window);
VIS_LDF(dsrc0, srcr);
VIS_LDF(dsrc1, srci);
dsrc0 = MUL32F(_MM_READ32_hi(dwin), _MM_READ32_hi(dsrc0));
dsrc1 = MUL32F(_MM_READ32_hi(dwin), _MM_READ32_hi(dsrc1));
fdst0 =
SSE2_fpackfix_r(
FREG(add, hi, dsrc0, lo, dsrc0, sub, hi, dsrc0, lo, dsrc0));
fdst1 =
SSE2_fpackfix_r(
FREG(add, hi, dsrc1, lo, dsrc1, sub, hi, dsrc1, lo, dsrc1));
VIS_STF(dstr, fdst0);
VIS_STF(dsti, fdst1);
break;
case 2:
gsr_shift = 1;
VIS_LDD(dwin, window);
dwin = SSE2_fmul8x16(fonebytwo, dwin);
VIS_LDD(dsrc, srcr);
VIS_LDD(dsrc3, srci);
MUL32_WIN(dsrc0, dsrc1, dwin, dsrc);
MUL32_WIN(dsrc2, dsrc3, dwin, dsrc3);
BUTT(dsrc, dsrc0, dsrc0, dsrc1);
BUTT(dst1, dsrc2, dsrc2, dsrc3);
dst =
SSE2_fpackfix_pair_r(FREG(add, hi, dsrc, lo, dsrc, sub, hi,
dsrc0, lo, dsrc2), FREG(sub, hi, dsrc, lo, dsrc, add, hi,
dsrc0, lo, dsrc2));
dst1 =
SSE2_fpackfix_pair_r(FREG(add, hi, dst1, lo, dst1, add, hi,
dsrc2, lo, dsrc0), FREG(sub, hi, dst1, lo, dst1, sub, hi,
dsrc2, lo, dsrc0));
VIS_STD(dstr, dst);
VIS_STD(dsti, dst1);
break;
case 3:
gsr_shift = 1;
VIS_LDD_2(dwin, dwin1, window);
dwin = SSE2_fmul8x16(foneby8, dwin);
dwin1 = SSE2_fmul8x16(foneby8, dwin1);
VIS_LDD_2(dsrc1, dsrc3, srcr);
VIS_LDD_2(dsrc5, dsrc7, srci);
MUL32_WIN(dsrc0, dsrc1, dwin, dsrc1);
MUL32_WIN(dsrc2, dsrc3, dwin1, dsrc3);
MUL32_WIN(dsrc4, dsrc5, dwin, dsrc5);
MUL32_WIN(dsrc6, dsrc7, dwin1, dsrc7);
BUTT(dst, dst1, dsrc0, dsrc2);
BUTT(dst2, dst3, dsrc1, dsrc3);
BUTT(dsrc0, dsrc1, dsrc4, dsrc6);
BUTT(dsrc2, dsrc3, dsrc5, dsrc7);
BUTT(dsrc4, dsrc5, dst, dst2);
BUTT(dsrc7, dsrc6, dst1, dsrc3);
BUTT(dst, dst1, dsrc0, dsrc2);
BUTT(dst2, dst3, dsrc1, dst3);
dsrc1 =
SSE2_fpackfix_pair(FREG(sub, lo, dsrc6, lo, dst2, add, lo,
dsrc6, lo, dst2), FREG(add, lo, dsrc7, lo, dst3, sub, lo,
dsrc7, lo, dst3));
gsr_shift = 3;
MUL32_HL(dsrc0, dsrc1, fsinpion4, dsrc1);
dsrc2 =
SSE2_fpackfix_pair_r(
FREG(add, hi, dsrc4, lo, dsrc4, add, hi, dsrc6, hi, dsrc0),
FREG(sub, hi, dsrc5, lo, dst1, sub, hi, dsrc7, hi, dsrc1));
dsrc3 =
SSE2_fpackfix_pair_r(
FREG(sub, hi, dsrc4, lo, dsrc4, sub, hi, dsrc6, hi, dsrc0),
FREG(add, hi, dsrc5, lo, dst1, add, hi, dsrc7, hi, dsrc1));
dsrc4 =
SSE2_fpackfix_pair_r(
FREG(add, hi, dst, lo, dst, add, hi, dst2, lo, dsrc0),
FREG(add, hi, dst1, lo, dsrc5, add, hi, dst3, lo, dsrc1));
dsrc5 =
SSE2_fpackfix_pair_r(
FREG(sub, hi, dst, lo, dst, sub, hi, dst2, lo, dsrc0),
FREG(sub, hi, dst1, lo, dsrc5, sub, hi, dst3, lo, dsrc1));
VIS_STD_2(dstr, dsrc2, dsrc3);
VIS_STD_2(dsti, dsrc4, dsrc5);
break;
case 4: {
__m128i tmp;
DCL_COMMON;
DCL_OUTVARR;
DCL_OUTVARI;
DCL_WINDOW;
PREP_OUTR;
PREP_OUTI;
LOAD_WINDOW;
LOAD_REAL;
LOAD_IMAG;
MUL_RWIN;
MUL_IWIN;
PROC_FIRST_INV;
TRANSPOSE4X4_REV_NEW(ar, br, cr, dr, ar, br, cr, dr);
TRANSPOSE4X4_REV_NEW(ai, bi, ci, di, ai, bi, ci, di);
LOAD_ROT;
PROC_LAST_INV;
PROC_LAST_END;
STORE_RE;
STORE_IM;
}
break;
default:
return (MLIB_FAILURE);
}
return (MLIB_SUCCESS);
}
static mlib_status
mlib_s_SignalFFTW_S16C_S16_0_4(
mlib_s16 *dstc,
const mlib_s16 *srcr,
const mlib_s16 *window,
mlib_s32 order)
{
__m128i dsrc, dsrc0, dsrc1, dsrc2, dsrc3, dst, dst1;
__m128i dsrc4, dsrc5, dst2, dst3, dwin, dwin1;
__m128i fdst0;
mlib_s32 fonebytwo = 1;
DEF_ADDER(fonebytwo);
mlib_s32 foneby8 = 3;
DEF_ADDER(foneby8);
__m128i fzero = _mm_setzero_si128();
__m128i fsinpion4 = _mm_set1_epi32(0x5A825A82);
mlib_s32 gsr_shift;
switch (order) {
case 0:
dstc[0] = (srcr[0] * window[0]) >> 15;
dstc[1] = 0;
break;
case 1:
gsr_shift = 0;
VIS_LDF(dwin, window);
VIS_LDF(dsrc0, srcr);
dsrc0 = MUL32F(_MM_READ32_hi(dwin), _MM_READ32_hi(dsrc0));
dst =
SSE2_fpackfix_pair_r(FREG_FZERO(add, hi, dsrc0, lo, dsrc0),
FREG_FZERO(sub, hi, dsrc0, lo, dsrc0));
VIS_STD(dstc, dst);
break;
case 2:
gsr_shift = 1;
VIS_LDD(dwin, window);
dwin = SSE2_fmul8x16(fonebytwo, dwin);
VIS_LDD(dsrc, srcr);
MUL32_WIN(dsrc0, dsrc1, dwin, dsrc);
BUTT(dsrc, dsrc0, dsrc0, dsrc1);
dst =
SSE2_fpackfix_pair_r(FREG_FZERO(add, hi, dsrc, lo, dsrc),
FREG(000, hi, dsrc0, 00, 00, sub, 00, fzero, lo, dsrc0));
dst1 =
SSE2_fpackfix_pair_r(FREG_FZERO(sub, hi, dsrc, lo, dsrc),
dsrc0);
VIS_STD_2(dstc, dst, dst1);
break;
case 3:
gsr_shift = 1;
VIS_LDD_2(dwin, dwin1, window);
dwin = SSE2_fmul8x16(foneby8, dwin);
dwin1 = SSE2_fmul8x16(foneby8, dwin1);
VIS_LDD_2(dsrc1, dsrc3, srcr);
MUL32_WIN(dsrc0, dsrc1, dwin, dsrc1);
MUL32_WIN(dsrc2, dsrc3, dwin1, dsrc3);
BUTT(dst, dst1, dsrc0, dsrc2);
BUTT(dst2, dst3, dsrc1, dsrc3);
BUTT(dsrc4, dsrc5, dst, dst2);
fdst0 =
SSE2_fpackfix(FREG(sub, lo, dst1, lo, dst3, add, lo, dst1,
lo, dst3));
gsr_shift = 2;
dsrc0 = MUL32F(fsinpion4, fdst0);
dsrc2 =
SSE2_fpackfix_pair_r(FREG_FZERO(add, hi, dsrc4, lo, dsrc4),
FREG(add, hi, dst1, hi, dsrc0, sub, 00,
AS_HL(sub, 00, fzero, hi, dst3), lo, dsrc0));
dsrc3 =
SSE2_fpackfix_pair_r(FREG(000, hi, dsrc5, 00, 00, sub, lo,
dst2, lo, dst), FREG(sub, hi, dst1, hi, dsrc0, sub, hi,
dst3, lo, dsrc0));
dsrc4 =
SSE2_fpackfix_pair_r(FREG_FZERO(sub, hi, dsrc4, lo, dsrc4),
FREG(sub, hi, dst1, hi, dsrc0, sub, lo, dsrc0, hi, dst3));
dsrc5 =
SSE2_fpackfix_pair_r(dsrc5,
FREG(add, hi, dst1, hi, dsrc0, add, hi, dst3, lo, dsrc0));
VIS_STD_4(dstc, dsrc2, dsrc3, dsrc4, dsrc5);
break;
case 4: {
__m128i reim0, reim1, reim2, reim3, reim4, reim5, reim6,
reim7;
DCL_COMMON;
DCL_OUTVARR;
DCL_WINDOW;
PREP_OUTC;
LOAD_WINDOW;
LOAD_REAL;
MUL_RWIN;
PROC_ONLYREAL_FIRST_DIR;
TRANSPOSE4X4_REV_NEW(ar, br, cr, dr, ar, br, cr, dr);
TRANSPOSE4X4_REV_NEW(ai, bi, ci, di, ai, bi, ci, di);
LOAD_ROT;
PROC_LAST_DIR;
PROC_LAST_END;
STORE_REIM;
}
break;
default:
return (MLIB_FAILURE);
}
return (MLIB_SUCCESS);
}
/* retrieve a thread context */
static void get_thread_context_ptrace( struct thread *thread, unsigned int flags, CONTEXT *context )
{
int pid = get_ptrace_pid(thread);
if (flags & CONTEXT_INTEGER)
{
#define XREG(x,y) if (ptrace( PTRACE_PEEKUSER, pid, (void*)(x<<2), &context->y) == -1) goto error;
#define IREG(x) if (ptrace( PTRACE_PEEKUSER, pid, (void*)(x<<2), &context->Gpr##x) == -1) goto error;
IREG(0); IREG(1); IREG(2); IREG(3); IREG(4); IREG(5); IREG(6);
IREG(7); IREG(8); IREG(9); IREG(10); IREG(11); IREG(12); IREG(13);
IREG(14); IREG(15); IREG(16); IREG(17); IREG(18); IREG(19);
IREG(20); IREG(21); IREG(22); IREG(23); IREG(24); IREG(25);
IREG(26); IREG(27); IREG(28); IREG(29); IREG(30); IREG(31);
#undef IREG
XREG(37,Xer);
XREG(38,Cr);
context->ContextFlags |= CONTEXT_INTEGER;
}
if (flags & CONTEXT_CONTROL)
{
XREG(32,Iar);
XREG(33,Msr);
XREG(35,Ctr);
XREG(36,Lr); /* 36 is LNK ... probably Lr ? */
context->ContextFlags |= CONTEXT_CONTROL;
}
if (flags & CONTEXT_FLOATING_POINT)
{
#define FREG(x) if (ptrace( PTRACE_PEEKUSER, pid, (void*)((48+x*2)<<2), &context->Fpr##x) == -1) goto error;
FREG(0);
FREG(1);
FREG(2);
FREG(3);
FREG(4);
FREG(5);
FREG(6);
FREG(7);
FREG(8);
FREG(9);
FREG(10);
FREG(11);
FREG(12);
FREG(13);
FREG(14);
FREG(15);
FREG(16);
FREG(17);
FREG(18);
FREG(19);
FREG(20);
FREG(21);
FREG(22);
FREG(23);
FREG(24);
FREG(25);
FREG(26);
FREG(27);
FREG(28);
FREG(29);
FREG(30);
FREG(31);
XREG((48+32*2),Fpscr);
context->ContextFlags |= CONTEXT_FLOATING_POINT;
}
return;
error:
file_set_error();
}
/* copy a context structure according to the flags */
void copy_context( CONTEXT *to, const CONTEXT *from, unsigned int flags )
{
if (flags & CONTEXT_CONTROL)
{
CREG(Msr);
CREG(Ctr);
CREG(Iar);
to->ContextFlags |= CONTEXT_CONTROL;
}
if (flags & CONTEXT_INTEGER)
{
IREG(0); IREG(1); IREG(2); IREG(3); IREG(4); IREG(5); IREG(6);
IREG(7); IREG(8); IREG(9); IREG(10); IREG(11); IREG(12); IREG(13);
IREG(14); IREG(15); IREG(16); IREG(17); IREG(18); IREG(19);
IREG(20); IREG(21); IREG(22); IREG(23); IREG(24); IREG(25);
IREG(26); IREG(27); IREG(28); IREG(29); IREG(30); IREG(31);
CREG(Xer);
CREG(Cr);
to->ContextFlags |= CONTEXT_INTEGER;
}
if (flags & CONTEXT_FLOATING_POINT)
{
FREG(0);
FREG(1);
FREG(2);
FREG(3);
FREG(4);
FREG(5);
FREG(6);
FREG(7);
FREG(8);
FREG(9);
FREG(10);
FREG(11);
FREG(12);
FREG(13);
FREG(14);
FREG(15);
FREG(16);
FREG(17);
FREG(18);
FREG(19);
FREG(20);
FREG(21);
FREG(22);
FREG(23);
FREG(24);
FREG(25);
FREG(26);
FREG(27);
FREG(28);
FREG(29);
FREG(30);
FREG(31);
CREG(Fpscr);
to->ContextFlags |= CONTEXT_FLOATING_POINT;
}
}
/* set a thread context */
static void set_thread_context_ptrace( struct thread *thread, unsigned int flags, const CONTEXT *context )
{
int pid = get_ptrace_pid(thread);
if (flags & CONTEXT_FULL)
{
if (flags & CONTEXT_INTEGER)
{
IREG(0); IREG(1); IREG(2); IREG(3); IREG(4); IREG(5); IREG(6);
IREG(7); IREG(8); IREG(9); IREG(10); IREG(11); IREG(12); IREG(13);
IREG(14); IREG(15); IREG(16); IREG(17); IREG(18); IREG(19);
IREG(20); IREG(21); IREG(22); IREG(23); IREG(24); IREG(25);
IREG(26); IREG(27); IREG(28); IREG(29); IREG(30); IREG(31);
XREG(37,Xer);
XREG(38,Cr);
}
if (flags & CONTEXT_CONTROL)
{
XREG(32,Iar);
XREG(33,Msr);
XREG(35,Ctr);
XREG(36,Lr);
}
}
if (flags & CONTEXT_FLOATING_POINT)
{
FREG(0);
FREG(1);
FREG(2);
FREG(3);
FREG(4);
FREG(5);
FREG(6);
FREG(7);
FREG(8);
FREG(9);
FREG(10);
FREG(11);
FREG(12);
FREG(13);
FREG(14);
FREG(15);
FREG(16);
FREG(17);
FREG(18);
FREG(19);
FREG(20);
FREG(21);
FREG(22);
FREG(23);
FREG(24);
FREG(25);
FREG(26);
FREG(27);
FREG(28);
FREG(29);
FREG(30);
FREG(31);
#undef FREG
XREG((48+32*2),Fpscr);
}
return;
error:
file_set_error();
}
{"A3", REGOFF(a3), RINT, 'X'},
{"A2", REGOFF(a2), RINT, 'X'},
{"A1", REGOFF(a1), RINT, 'X'},
{"A0", REGOFF(a0), RINT, 'X'},
{"R7", REGOFF(r7), RINT, 'X'},
{"R6", REGOFF(r6), RINT, 'X'},
{"R5", REGOFF(r5), RINT, 'X'},
{"R4", REGOFF(r4), RINT, 'X'},
{"R3", REGOFF(r3), RINT, 'X'},
{"R2", REGOFF(r2), RINT, 'X'},
{"R1", REGOFF(r1), RINT, 'X'},
{"R0", REGOFF(r0), RINT, 'X'},
{"FPCR", FCTL(0), RFLT, 'X'},
{"FPSR", FCTL(1), RFLT, 'X'},
{"FPIAR", FCTL(2), RFLT, 'X'},
{"F0", FREG(0), RFLT, '8'},
{"F1", FREG(1), RFLT, '8'},
{"F2", FREG(2), RFLT, '8'},
{"F3", FREG(3), RFLT, '8'},
{"F4", FREG(4), RFLT, '8'},
{"F5", FREG(5), RFLT, '8'},
{"F6", FREG(6), RFLT, '8'},
{"F7", FREG(7), RFLT, '8'},
{0}
};
Mach m68020 =
{
"68020",
M68020, /* machine type */
m68020reglist, /* register list */
void decode_opc(DisasContext * ctx)
{
#if 0
fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
#endif
switch (ctx->opcode) {
case 0x0019: /* div0u */
gen_op_div0u();
return;
case 0x000b: /* rts */
CHECK_NOT_DELAY_SLOT gen_op_rts();
ctx->flags |= DELAY_SLOT;
ctx->delayed_pc = (uint32_t) - 1;
return;
case 0x0028: /* clrmac */
gen_op_clrmac();
return;
case 0x0048: /* clrs */
gen_op_clrs();
return;
case 0x0008: /* clrt */
gen_op_clrt();
return;
case 0x0038: /* ldtlb */
assert(0); /* XXXXX */
return;
case 0x004b: /* rte */
CHECK_NOT_DELAY_SLOT gen_op_rte();
ctx->flags |= DELAY_SLOT;
ctx->delayed_pc = (uint32_t) - 1;
return;
case 0x0058: /* sets */
gen_op_sets();
return;
case 0x0018: /* sett */
gen_op_sett();
return;
case 0xfbfb: /* frchg */
gen_op_frchg();
ctx->flags |= MODE_CHANGE;
return;
case 0xf3fb: /* fschg */
gen_op_fschg();
ctx->flags |= MODE_CHANGE;
return;
case 0x0009: /* nop */
return;
case 0x001b: /* sleep */
assert(0); /* XXXXX */
return;
}
switch (ctx->opcode & 0xf000) {
case 0x1000: /* mov.l Rm,@(disp,Rn) */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_addl_imm_T1(B3_0 * 4);
gen_op_stl_T0_T1(ctx);
return;
case 0x5000: /* mov.l @(disp,Rm),Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_addl_imm_T0(B3_0 * 4);
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0xe000: /* mov.l #imm,Rn */
gen_op_movl_imm_rN(B7_0s, REG(B11_8));
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2);
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0xd000: /* mov.l @(disp,PC),Rn */
gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3);
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x7000: /* add.l #imm,Rn */
gen_op_add_imm_rN(B7_0s, REG(B11_8));
return;
case 0xa000: /* bra disp */
CHECK_NOT_DELAY_SLOT
gen_op_bra(ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2);
ctx->flags |= DELAY_SLOT;
return;
case 0xb000: /* bsr disp */
CHECK_NOT_DELAY_SLOT
gen_op_bsr(ctx->pc + 4, ctx->delayed_pc =
ctx->pc + 4 + B11_0s * 2);
ctx->flags |= DELAY_SLOT;
return;
}
switch (ctx->opcode & 0xf00f) {
case 0x6003: /* mov Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x2000: /* mov.b Rm,@Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stb_T0_T1(ctx);
return;
case 0x2001: /* mov.w Rm,@Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stw_T0_T1(ctx);
return;
case 0x2002: /* mov.l Rm,@Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stl_T0_T1(ctx);
return;
case 0x6000: /* mov.b @Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldb_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x6001: /* mov.w @Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x6002: /* mov.l @Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x2004: /* mov.b Rm,@-Rn */
gen_op_dec1_rN(REG(B11_8));
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stb_T0_T1(ctx);
return;
case 0x2005: /* mov.w Rm,@-Rn */
gen_op_dec2_rN(REG(B11_8));
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stw_T0_T1(ctx);
return;
case 0x2006: /* mov.l Rm,@-Rn */
gen_op_dec4_rN(REG(B11_8));
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stl_T0_T1(ctx);
return;
case 0x6004: /* mov.b @Rm+,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldb_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
gen_op_inc1_rN(REG(B7_4));
return;
case 0x6005: /* mov.w @Rm+,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
gen_op_inc2_rN(REG(B7_4));
return;
case 0x6006: /* mov.l @Rm+,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
gen_op_inc4_rN(REG(B7_4));
return;
case 0x0004: /* mov.b Rm,@(R0,Rn) */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stb_T0_T1(ctx);
return;
case 0x0005: /* mov.w Rm,@(R0,Rn) */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stw_T0_T1(ctx);
return;
case 0x0006: /* mov.l Rm,@(R0,Rn) */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stl_T0_T1(ctx);
return;
case 0x000c: /* mov.b @(R0,Rm),Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldb_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x000d: /* mov.w @(R0,Rm),Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x000e: /* mov.l @(R0,Rm),Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x6008: /* swap.b Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_swapb_T0();
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x6009: /* swap.w Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_swapw_T0();
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x200d: /* xtrct Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_xtrct_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x300c: /* add Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_T0_rN(REG(B11_8));
return;
case 0x300e: /* addc Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_addc_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x300f: /* addv Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_addv_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x2009: /* and Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_and_T0_rN(REG(B11_8));
return;
case 0x3000: /* cmp/eq Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_cmp_eq_T0_T1();
return;
case 0x3003: /* cmp/ge Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_cmp_ge_T0_T1();
return;
case 0x3007: /* cmp/gt Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_cmp_gt_T0_T1();
return;
case 0x3006: /* cmp/hi Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_cmp_hi_T0_T1();
return;
case 0x3002: /* cmp/hs Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_cmp_hs_T0_T1();
return;
case 0x200c: /* cmp/str Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_cmp_str_T0_T1();
return;
case 0x2007: /* div0s Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_div0s_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x3004: /* div1 Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_div1_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x300d: /* dmuls.l Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_dmulsl_T0_T1();
return;
case 0x3005: /* dmulu.l Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_dmulul_T0_T1();
return;
case 0x600e: /* exts.b Rm,Rn */
gen_op_movb_rN_T0(REG(B7_4));
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x600f: /* exts.w Rm,Rn */
gen_op_movw_rN_T0(REG(B7_4));
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x600c: /* extu.b Rm,Rn */
gen_op_movub_rN_T0(REG(B7_4));
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x600d: /* extu.w Rm,Rn */
gen_op_movuw_rN_T0(REG(B7_4));
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x000f: /* mac.l @Rm+,@Rn- */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_T1();
gen_op_movl_rN_T1(REG(B7_4));
gen_op_ldl_T0_T0(ctx);
gen_op_macl_T0_T1();
gen_op_inc4_rN(REG(B7_4));
gen_op_inc4_rN(REG(B11_8));
return;
case 0x400f: /* mac.w @Rm+,@Rn+ */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_T1();
gen_op_movl_rN_T1(REG(B7_4));
gen_op_ldl_T0_T0(ctx);
gen_op_macw_T0_T1();
gen_op_inc2_rN(REG(B7_4));
gen_op_inc2_rN(REG(B11_8));
return;
case 0x0007: /* mul.l Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_mull_T0_T1();
return;
case 0x200f: /* muls.w Rm,Rn */
gen_op_movw_rN_T0(REG(B7_4));
gen_op_movw_rN_T1(REG(B11_8));
gen_op_mulsw_T0_T1();
return;
case 0x200e: /* mulu.w Rm,Rn */
gen_op_movuw_rN_T0(REG(B7_4));
gen_op_movuw_rN_T1(REG(B11_8));
gen_op_muluw_T0_T1();
return;
case 0x600b: /* neg Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_neg_T0();
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x600a: /* negc Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_negc_T0();
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x6007: /* not Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_not_T0();
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0x200b: /* or Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_or_T0_rN(REG(B11_8));
return;
case 0x400c: /* shad Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_shad_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x400d: /* shld Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_shld_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x3008: /* sub Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_sub_T0_rN(REG(B11_8));
return;
case 0x300a: /* subc Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_subc_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x300b: /* subv Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_subv_T0_T1();
gen_op_movl_T1_rN(REG(B11_8));
return;
case 0x2008: /* tst Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_tst_T0_T1();
return;
case 0x200a: /* xor Rm,Rn */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_xor_T0_rN(REG(B11_8));
return;
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0110)
break; /* illegal instruction */
gen_op_fmov_drN_DT0(DREG(B7_4));
gen_op_fmov_DT0_drN(DREG(B11_8));
} else {
gen_op_fmov_frN_FT0(FREG(B7_4));
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010)
break; /* illegal instruction */
gen_op_fmov_drN_DT0(DREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else {
gen_op_fmov_frN_FT0(FREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfl_FT0_T1(ctx);
}
return;
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
gen_op_fmov_DT0_drN(DREG(B11_8));
} else {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfl_T0_FT0(ctx);
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfq_T0_DT0(ctx);
gen_op_fmov_DT0_drN(DREG(B11_8));
gen_op_inc8_rN(REG(B7_4));
} else {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_ldfl_T0_FT0(ctx);
gen_op_fmov_FT0_frN(FREG(B11_8));
gen_op_inc4_rN(REG(B7_4));
}
return;
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_dec8_rN(REG(B11_8));
gen_op_fmov_drN_DT0(DREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfq_DT0_T1(ctx);
} else {
gen_op_dec4_rN(REG(B11_8));
gen_op_fmov_frN_FT0(FREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_stfl_FT0_T1(ctx);
}
return;
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0100)
break; /* illegal instruction */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldfq_T0_DT0(ctx);
gen_op_fmov_DT0_drN(DREG(B11_8));
} else {
gen_op_movl_rN_T0(REG(B7_4));
gen_op_add_rN_T0(REG(0));
gen_op_ldfl_T0_FT0(ctx);
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
if (ctx->fpscr & FPSCR_SZ) {
if (ctx->opcode & 0x0010)
break; /* illegal instruction */
gen_op_fmov_drN_DT0(DREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stfq_DT0_T1(ctx);
} else {
gen_op_fmov_frN_FT0(FREG(B7_4));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_add_rN_T1(REG(0));
gen_op_stfl_FT0_T1(ctx);
}
return;
case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
if (ctx->fpscr & FPSCR_PR) {
if (ctx->opcode & 0x0110)
break; /* illegal instruction */
gen_op_fmov_drN_DT1(DREG(B7_4));
gen_op_fmov_drN_DT0(DREG(B11_8));
}
else {
gen_op_fmov_frN_FT1(FREG(B7_4));
gen_op_fmov_frN_FT0(FREG(B11_8));
}
switch (ctx->opcode & 0xf00f) {
case 0xf000: /* fadd Rm,Rn */
ctx->fpscr & FPSCR_PR ? gen_op_fadd_DT() : gen_op_fadd_FT();
break;
case 0xf001: /* fsub Rm,Rn */
ctx->fpscr & FPSCR_PR ? gen_op_fsub_DT() : gen_op_fsub_FT();
break;
case 0xf002: /* fmul Rm,Rn */
ctx->fpscr & FPSCR_PR ? gen_op_fmul_DT() : gen_op_fmul_FT();
break;
case 0xf003: /* fdiv Rm,Rn */
ctx->fpscr & FPSCR_PR ? gen_op_fdiv_DT() : gen_op_fdiv_FT();
break;
case 0xf004: /* fcmp/eq Rm,Rn */
return;
case 0xf005: /* fcmp/gt Rm,Rn */
return;
}
if (ctx->fpscr & FPSCR_PR) {
gen_op_fmov_DT0_drN(DREG(B11_8));
}
else {
gen_op_fmov_FT0_frN(FREG(B11_8));
}
return;
}
switch (ctx->opcode & 0xff00) {
case 0xc900: /* and #imm,R0 */
gen_op_and_imm_rN(B7_0, REG(0));
return;
case 0xcd00: /* and.b #imm,@(R0+GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
gen_op_movl_T0_T1();
gen_op_ldb_T0_T0(ctx);
gen_op_and_imm_T0(B7_0);
gen_op_stb_T0_T1(ctx);
return;
case 0x8b00: /* bf label */
CHECK_NOT_DELAY_SLOT
gen_conditional_jump(ctx, ctx->pc + 2,
ctx->pc + 4 + B7_0s * 2);
ctx->flags |= BRANCH_CONDITIONAL;
return;
case 0x8f00: /* bf/s label */
CHECK_NOT_DELAY_SLOT
gen_op_bf_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2);
ctx->flags |= DELAY_SLOT_CONDITIONAL;
return;
case 0x8900: /* bt label */
CHECK_NOT_DELAY_SLOT
gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
ctx->pc + 2);
ctx->flags |= BRANCH_CONDITIONAL;
return;
case 0x8d00: /* bt/s label */
CHECK_NOT_DELAY_SLOT
gen_op_bt_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2);
ctx->flags |= DELAY_SLOT_CONDITIONAL;
return;
case 0x8800: /* cmp/eq #imm,R0 */
gen_op_movl_rN_T0(REG(0));
gen_op_cmp_eq_imm_T0(B7_0s);
return;
case 0xc400: /* mov.b @(disp,GBR),R0 */
gen_op_stc_gbr_T0();
gen_op_addl_imm_T0(B7_0);
gen_op_ldb_T0_T0(ctx);
gen_op_movl_T0_rN(REG(0));
return;
case 0xc500: /* mov.w @(disp,GBR),R0 */
gen_op_stc_gbr_T0();
gen_op_addl_imm_T0(B7_0);
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(0));
return;
case 0xc600: /* mov.l @(disp,GBR),R0 */
gen_op_stc_gbr_T0();
gen_op_addl_imm_T0(B7_0);
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(0));
return;
case 0xc000: /* mov.b R0,@(disp,GBR) */
gen_op_stc_gbr_T0();
gen_op_addl_imm_T0(B7_0);
gen_op_movl_T0_T1();
gen_op_movl_rN_T0(REG(0));
gen_op_stb_T0_T1(ctx);
return;
case 0xc100: /* mov.w R0,@(disp,GBR) */
gen_op_stc_gbr_T0();
gen_op_addl_imm_T0(B7_0);
gen_op_movl_T0_T1();
gen_op_movl_rN_T0(REG(0));
gen_op_stw_T0_T1(ctx);
return;
case 0xc200: /* mov.l R0,@(disp,GBR) */
gen_op_stc_gbr_T0();
gen_op_addl_imm_T0(B7_0);
gen_op_movl_T0_T1();
gen_op_movl_rN_T0(REG(0));
gen_op_stl_T0_T1(ctx);
return;
case 0x8000: /* mov.b R0,@(disp,Rn) */
gen_op_movl_rN_T0(REG(0));
gen_op_movl_rN_T1(REG(B7_4));
gen_op_addl_imm_T1(B3_0);
gen_op_stb_T0_T1(ctx);
return;
case 0x8100: /* mov.w R0,@(disp,Rn) */
gen_op_movl_rN_T0(REG(0));
gen_op_movl_rN_T1(REG(B7_4));
gen_op_addl_imm_T1(B3_0 * 2);
gen_op_stw_T0_T1(ctx);
return;
case 0x8400: /* mov.b @(disp,Rn),R0 */
gen_op_movl_rN_T0(REG(0));
gen_op_movl_rN_T1(REG(B7_4));
gen_op_addl_imm_T1(B3_0);
gen_op_stb_T0_T1(ctx);
return;
case 0x8500: /* mov.w @(disp,Rn),R0 */
gen_op_movl_rN_T0(REG(B7_4));
gen_op_addl_imm_T0(B3_0 * 2);
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(0));
return;
case 0xc700: /* mova @(disp,PC),R0 */
gen_op_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3,
REG(0));
return;
case 0xcb00: /* or #imm,R0 */
gen_op_or_imm_rN(B7_0, REG(0));
return;
case 0xcf00: /* or.b #imm,@(R0+GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
gen_op_movl_T0_T1();
gen_op_ldb_T0_T0(ctx);
gen_op_or_imm_T0(B7_0);
gen_op_stb_T0_T1(ctx);
return;
case 0xc300: /* trapa #imm */
CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc);
gen_op_trapa(B7_0);
ctx->flags |= BRANCH;
return;
case 0xc800: /* tst #imm,R0 */
gen_op_tst_imm_rN(B7_0, REG(0));
return;
case 0xcc00: /* tst #imm,@(R0+GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
gen_op_ldb_T0_T0(ctx);
gen_op_tst_imm_T0(B7_0);
return;
case 0xca00: /* xor #imm,R0 */
gen_op_xor_imm_rN(B7_0, REG(0));
return;
case 0xce00: /* xor.b #imm,@(R0+GBR) */
gen_op_movl_rN_T0(REG(0));
gen_op_addl_GBR_T0();
gen_op_movl_T0_T1();
gen_op_ldb_T0_T0(ctx);
gen_op_xor_imm_T0(B7_0);
gen_op_stb_T0_T1(ctx);
return;
}
switch (ctx->opcode & 0xf08f) {
case 0x408e: /* ldc Rm,Rn_BANK */
gen_op_movl_rN_rN(REG(B11_8), ALTREG(B6_4));
return;
case 0x4087: /* ldc.l @Rm+,Rn_BANK */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(ALTREG(B6_4));
gen_op_inc4_rN(REG(B11_8));
return;
case 0x0082: /* stc Rm_BANK,Rn */
gen_op_movl_rN_rN(ALTREG(B6_4), REG(B11_8));
return;
case 0x4083: /* stc.l Rm_BANK,@-Rn */
gen_op_dec4_rN(REG(B11_8));
gen_op_movl_rN_T1(REG(B11_8));
gen_op_movl_rN_T0(ALTREG(B6_4));
gen_op_stl_T0_T1(ctx);
return;
}
switch (ctx->opcode & 0xf0ff) {
case 0x0023: /* braf Rn */
CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
gen_op_braf_T0(ctx->pc + 4);
ctx->flags |= DELAY_SLOT;
ctx->delayed_pc = (uint32_t) - 1;
return;
case 0x0003: /* bsrf Rn */
CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
gen_op_bsrf_T0(ctx->pc + 4);
ctx->flags |= DELAY_SLOT;
ctx->delayed_pc = (uint32_t) - 1;
return;
case 0x4015: /* cmp/pl Rn */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_cmp_pl_T0();
return;
case 0x4011: /* cmp/pz Rn */
gen_op_movl_rN_T0(REG(B11_8));
gen_op_cmp_pz_T0();
return;
case 0x4010: /* dt Rn */
gen_op_dt_rN(REG(B11_8));
return;
case 0x402b: /* jmp @Rn */
CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
gen_op_jmp_T0();
ctx->flags |= DELAY_SLOT;
ctx->delayed_pc = (uint32_t) - 1;
return;
case 0x400b: /* jsr @Rn */
CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
gen_op_jsr_T0(ctx->pc + 4);
ctx->flags |= DELAY_SLOT;
ctx->delayed_pc = (uint32_t) - 1;
return;
#define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \
case ldnum: \
gen_op_movl_rN_T0 (REG(B11_8)); \
gen_op_##ldop##_T0_##reg (); \
extrald \
return; \
case ldpnum: \
gen_op_movl_rN_T0 (REG(B11_8)); \
gen_op_ldl_T0_T0 (ctx); \
gen_op_inc4_rN (REG(B11_8)); \
gen_op_##ldop##_T0_##reg (); \
extrald \
return; \
case stnum: \
gen_op_##stop##_##reg##_T0 (); \
gen_op_movl_T0_rN (REG(B11_8)); \
return; \
case stpnum: \
gen_op_##stop##_##reg##_T0 (); \
gen_op_dec4_rN (REG(B11_8)); \
gen_op_movl_rN_T1 (REG(B11_8)); \
gen_op_stl_T0_T1 (ctx); \
return;
LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->flags |=
MODE_CHANGE;)
LDST(gbr, 0x401e, 0x4017, ldc, 0x0012, 0x4013, stc,)
LDST(vbr, 0x402e, 0x4027, ldc, 0x0022, 0x4023, stc,)
LDST(ssr, 0x403e, 0x4037, ldc, 0x0032, 0x4033, stc,)
LDST(spc, 0x404e, 0x4047, ldc, 0x0042, 0x4043, stc,)
LDST(dbr, 0x40fa, 0x40f6, ldc, 0x00fa, 0x40f2, stc,)
LDST(mach, 0x400a, 0x4006, lds, 0x000a, 0x4002, sts,)
LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,)
LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,)
LDST(fpul, 0x405a, 0x4056, lds, 0x005a, 0x4052, sts,)
LDST(fpscr, 0x406a, 0x4066, lds, 0x006a, 0x4062, sts, ctx->flags |=
MODE_CHANGE;)
case 0x00c3: /* movca.l R0,@Rm */
u_int __attribute__((__section__(".stack_tsk2"))) stack2[DEFAULT_STACK_SIZE];
u_int __attribute__((__section__(".stack_tsk3"))) stack3[DEFAULT_STACK_SIZE];
u_int __attribute__((__section__(".stack_tsk4"))) stack4[128];
/**********************************************************************
* ---------------------- TASK DESCRIPTOR SECTION ---------------------
**********************************************************************/
const unsigned int descromarea;
const TCB TCB_const_list[] =
{
/*******************************************************************
* -------------------------- Task 0 -------------------------------
*******************************************************************/
{
SREG(stack0), /* Stack_register */
FREG(stack0), /* Frame_register */
TASK0, /* StartAddress */
stack0, /* StackAddress */
sizeof(stack0), /* StackSize */
TASK0_ID, /* TaskID */
TASK0_PRIO, /* Priority */
NONE, /* EventWaited */
NONE, /* EventReceived */
READY, /* State */
EXTENDED, /* Type */
0, /* Time */
0, /* kernelState_copy */
NULL /* next */
},
/*******************************************************************
* -------------------------- Task 1 -------------------------------
