/**
* @brief Performs the SRAM device initialization sequence
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param Timing: Pointer to SRAM control timing structure
* @param ExtTiming: Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if(hsram == NULL)
{
return HAL_ERROR;
}
if(hsram->State == HAL_SRAM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
}
/* Initialize SRAM control Interface */
FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
/* Initialize SRAM timing Interface */
FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
return HAL_OK;
}
/**
* @brief Initializes the FSMC
* @param None
* @retval None
*/
static void prvLCD_FSMCConfig()
{
/*-- FSMC Configuration ---------------------------------*/
/* The FSMC NOR Flash/SRAM bank is suitable for MCU parallel color LCD interfaces */
FSMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitStructure;
FSMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingInitStructure;
/* FSMC_NORSRAM_BANK1 timing configuration, see reference manual rev 7 p. 1528 for min/max values */
FSMC_NORSRAM_TimingInitStructure.AddressSetupTime = 4;
FSMC_NORSRAM_TimingInitStructure.AddressHoldTime = 1;
FSMC_NORSRAM_TimingInitStructure.DataSetupTime = 3;
FSMC_NORSRAM_TimingInitStructure.BusTurnAroundDuration = 0;
FSMC_NORSRAM_TimingInitStructure.CLKDivision = 2;
FSMC_NORSRAM_TimingInitStructure.DataLatency = 2;
FSMC_NORSRAM_TimingInitStructure.AccessMode = FSMC_ACCESS_MODE_B;
/* FSMC_NORSRAM_BANK1 configured as follows:
* - Data/Address MUX = Disable
* - Memory Type = SRAM
* - Data Width = 16bit
* - Write Operation = Enable
* - Asynchronous Wait = Disable
* - Extended Mode = Disable
*/
FSMC_NORSRAM_InitStructure.NSBank = FSMC_NORSRAM_BANK1;
FSMC_NORSRAM_InitStructure.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
FSMC_NORSRAM_InitStructure.MemoryType = FSMC_MEMORY_TYPE_SRAM; // NOR???
FSMC_NORSRAM_InitStructure.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
FSMC_NORSRAM_InitStructure.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
FSMC_NORSRAM_InitStructure.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
FSMC_NORSRAM_InitStructure.WrapMode = FSMC_WRAP_MODE_DISABLE;
FSMC_NORSRAM_InitStructure.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
FSMC_NORSRAM_InitStructure.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
FSMC_NORSRAM_InitStructure.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; // ENABLE, LCD_WAIT???
FSMC_NORSRAM_InitStructure.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
FSMC_NORSRAM_InitStructure.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
FSMC_NORSRAM_InitStructure.WriteBurst = FSMC_WRITE_BURST_DISABLE;
/* FSMC NORSRAM bank control configuration */
FSMC_NORSRAM_Init(FSMC_NORSRAM_DEVICE, &FSMC_NORSRAM_InitStructure);
/* FSMC NORSRAM bank timing configuration */
FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_DEVICE, &FSMC_NORSRAM_TimingInitStructure, 0);
/* Enable FSMC_NORSRAM_BANK1 */
FSMC_NORSRAMCmd(FSMC_NORSRAM_BANK1, ENABLE);
}
/**
* @brief Perform the NOR memory Initialization sequence
* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Timing: pointer to NOR control timing structure
* @param ExtTiming: pointer to NOR extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the NOR handle parameter */
if(hnor == NULL)
{
return HAL_ERROR;
}
if(hnor->State == HAL_NOR_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hnor->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
}
/* Initialize NOR control Interface */
FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
/* Initialize NOR timing Interface */
FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
/* Initialize NOR Memory Data Width*/
if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
{
uwNORMemoryDataWidth = NOR_MEMORY_8B;
}
else
{
uwNORMemoryDataWidth = NOR_MEMORY_16B;
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
return HAL_OK;
}
