void BOARD::SynchronizeNetsAndNetClasses()
{
NETCLASSES& netClasses = m_designSettings.m_NetClasses;
NETCLASSPTR defaultNetClass = netClasses.GetDefault();
// set all NETs to the default NETCLASS, then later override some
// as we go through the NETCLASSes.
for( NETINFO_LIST::iterator net( m_NetInfo.begin() ), netEnd( m_NetInfo.end() );
net != netEnd; ++net )
{
net->SetClass( defaultNetClass );
}
// Add netclass name and pointer to nets. If a net is in more than one netclass,
// set the net's name and pointer to only the first netclass. Subsequent
// and therefore bogus netclass memberships will be deleted in logic below this loop.
for( NETCLASSES::iterator clazz = netClasses.begin(); clazz != netClasses.end(); ++clazz )
{
NETCLASSPTR netclass = clazz->second;
for( NETCLASS::const_iterator member = netclass->begin(); member != netclass->end(); ++member )
{
const wxString& netname = *member;
// although this overall function seems to be adequately fast,
// FindNet( wxString ) uses now a fast binary search and is fast
// event for large net lists
NETINFO_ITEM* net = FindNet( netname );
if( net && net->GetClassName() == NETCLASS::Default )
{
net->SetClass( netclass );
}
}
}
// Finally, make sure that every NET is in a NETCLASS, even if that
// means the Default NETCLASS. And make sure that all NETCLASSes do not
// contain netnames that do not exist, by deleting all netnames from
// every netclass and re-adding them.
for( NETCLASSES::iterator clazz = netClasses.begin(); clazz != netClasses.end(); ++clazz )
{
NETCLASSPTR netclass = clazz->second;
netclass->Clear();
}
defaultNetClass->Clear();
for( NETINFO_LIST::iterator net( m_NetInfo.begin() ), netEnd( m_NetInfo.end() );
net != netEnd; ++net )
{
const wxString& classname = net->GetClassName();
// because of the std:map<> this should be fast, and because of
// prior logic, netclass should not be NULL.
NETCLASSPTR netclass = netClasses.Find( classname );
wxASSERT( netclass );
netclass->Add( net->GetNetname() );
}
// Set initial values for custom track width & via size to match the default netclass settings
m_designSettings.UseCustomTrackViaSize( false );
m_designSettings.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
m_designSettings.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
m_designSettings.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
}
void BOARD::SynchronizeNetsAndNetClasses()
{
// D(printf("start\n");) // simple performance/timing indicator.
// set all NETs to the default NETCLASS, then later override some
// as we go through the NETCLASSes.
int count = m_NetInfo.GetNetCount();
for( int i=0; i<count; ++i )
{
NETINFO_ITEM* net = FindNet( i );
if( net )
net->SetClass( m_NetClasses.GetDefault() );
}
// Add netclass name and pointer to nets. If a net is in more than one netclass,
// set the net's name and pointer to only the first netclass. Subsequent
// and therefore bogus netclass memberships will be deleted in logic below this loop.
for( NETCLASSES::iterator clazz=m_NetClasses.begin(); clazz!=m_NetClasses.end(); ++clazz )
{
NETCLASS* netclass = clazz->second;
for( NETCLASS::iterator member = netclass->begin(); member!=netclass->end(); ++member )
{
const wxString& netname = *member;
// although this overall function seems to be adequately fast,
// FindNet( wxString ) uses now a fast binary search and is fast
// event for large net lists
NETINFO_ITEM* net = FindNet( netname );
if( net && net->GetClassName() == NETCLASS::Default )
{
net->SetClass( netclass );
}
}
}
// Finally, make sure that every NET is in a NETCLASS, even if that
// means the Default NETCLASS. And make sure that all NETCLASSes do not
// contain netnames that do not exist, by deleting all netnames from
// every netclass and re-adding them.
for( NETCLASSES::iterator clazz=m_NetClasses.begin(); clazz!=m_NetClasses.end(); ++clazz )
{
NETCLASS* netclass = clazz->second;
netclass->Clear();
}
m_NetClasses.GetDefault()->Clear();
for( int i=0; i<count; ++i )
{
NETINFO_ITEM* net = FindNet( i );
if( net )
{
const wxString& classname = net->GetClassName();
// because of the std:map<> this should be fast, and because of
// prior logic, netclass should not be NULL.
NETCLASS* netclass = m_NetClasses.Find( classname );
wxASSERT( netclass );
netclass->Add( net->GetNetname() );
}
}
// D(printf("stop\n");)
}
/**
* Function Test_Connection_To_Copper_Areas
* init .m_ZoneSubnet parameter in tracks and pads according to the connections to areas found
* @param aNetcode = netcode to analyse. if -1, analyse all nets
*/
void BOARD::Test_Connections_To_Copper_Areas( int aNetcode )
{
// list of pads and tracks candidates on this layer and on this net.
// It is static to avoid multiple memory realloc.
static std::vector <BOARD_CONNECTED_ITEM*> candidates;
// clear .m_ZoneSubnet parameter for pads
for( MODULE* module = m_Modules; module; module = module->Next() )
{
for( D_PAD* pad = module->Pads(); pad; pad = pad->Next() )
if( aNetcode < 0 || aNetcode == pad->GetNetCode() )
pad->SetZoneSubNet( 0 );
}
// clear .m_ZoneSubnet parameter for tracks and vias
for( TRACK* track = m_Track; track; track = track->Next() )
{
if( aNetcode < 0 || aNetcode == track->GetNetCode() )
track->SetZoneSubNet( 0 );
}
// examine all zones, net by net:
int subnet = 0;
// Build zones candidates list
std::vector<ZONE_CONTAINER*> zones_candidates;
zones_candidates.reserve( GetAreaCount() );
for( int index = 0; index < GetAreaCount(); index++ )
{
ZONE_CONTAINER* zone = GetArea( index );
if( !zone->IsOnCopperLayer() )
continue;
if( aNetcode >= 0 && aNetcode != zone->GetNetCode() )
continue;
if( zone->GetFilledPolysList().GetCornersCount() == 0 )
continue;
zones_candidates.push_back( zone );
}
// sort them by netcode then vertices count.
// For a given net, examine the smaller zones first slightly speed up calculation
// (25% faster)
// this is only noticeable with very large boards and depends on board zones topology
// This is due to the fact some items are connected by small zones ares,
// before examining large zones areas and these items are not tested after a connection is found
sort( zones_candidates.begin(), zones_candidates.end(), sort_areas );
int oldnetcode = -1;
for( unsigned idx = 0; idx < zones_candidates.size(); idx++ )
{
ZONE_CONTAINER* zone = zones_candidates[idx];
int netcode = zone->GetNetCode();
// Build a list of candidates connected to the net:
// At this point, layers are not considered, because areas on different layers can
// be connected by a via or a pad.
// (because zones are sorted by netcode, there is made only once per net)
NETINFO_ITEM* net = FindNet( netcode );
wxASSERT( net );
if( net == NULL )
continue;
if( oldnetcode != netcode )
{
oldnetcode = netcode;
candidates.clear();
// Build the list of pads candidates connected to the net:
candidates.reserve( net->m_PadInNetList.size() );
for( unsigned ii = 0; ii < net->m_PadInNetList.size(); ii++ )
candidates.push_back( net->m_PadInNetList[ii] );
// Build the list of track candidates connected to the net:
TRACK* track = m_Track.GetFirst()->GetStartNetCode( netcode );
for( ; track; track = track->Next() )
{
if( track->GetNetCode() != netcode )
break;
candidates.push_back( track );
}
}
// test if a candidate is inside a filled area of this zone
unsigned indexstart = 0, indexend;
const CPOLYGONS_LIST& polysList = zone->GetFilledPolysList();
for( indexend = 0; indexend < polysList.GetCornersCount(); indexend++ )
{
// end of a filled sub-area found
if( polysList.IsEndContour( indexend ) )
{
subnet++;
EDA_RECT bbox = zone->CalculateSubAreaBoundaryBox( indexstart, indexend );
for( unsigned ic = 0; ic < candidates.size(); ic++ )
{
// test if this area is connected to a board item:
BOARD_CONNECTED_ITEM* item = candidates[ic];
if( item->GetZoneSubNet() == subnet ) // Already merged
continue;
if( !item->IsOnLayer( zone->GetLayer() ) )
continue;
wxPoint pos1, pos2;
if( item->Type() == PCB_PAD_T )
{
// For pads we use the shape position instead of
// the pad position, because the zones are connected
// to the center of the shape, not the pad position
// (this is important for pads with thermal relief)
pos1 = pos2 = ( (D_PAD*) item )->ShapePos();
}
else if( item->Type() == PCB_VIA_T )
{
const VIA *via = static_cast<const VIA*>( item );
pos1 = via->GetStart();
pos2 = pos1;
}
else if( item->Type() == PCB_TRACE_T )
{
const TRACK *trk = static_cast<const TRACK*>( item );
pos1 = trk->GetStart();
pos2 = trk->GetEnd();
}
else
{
continue;
}
bool connected = false;
if( bbox.Contains( pos1 ) )
{
if( TestPointInsidePolygon( polysList, indexstart,
indexend, pos1.x, pos1.y ) )
connected = true;
}
if( !connected && (pos1 != pos2 ) )
{
if( bbox.Contains( pos2 ) )
{
if( TestPointInsidePolygon( polysList,
indexstart, indexend,
pos2.x, pos2.y ) )
connected = true;
}
}
if( connected )
{
// Set ZoneSubnet to the current subnet value.
// If the previous subnet is not 0, merge all items with old subnet
// to the new one
int old_subnet = item->GetZoneSubNet();
item->SetZoneSubNet( subnet );
// Merge previous subnet with the current
if( (old_subnet > 0) && (old_subnet != subnet) )
{
for( unsigned jj = 0; jj < candidates.size(); jj++ )
{
BOARD_CONNECTED_ITEM* item_to_merge = candidates[jj];
if( old_subnet == item_to_merge->GetZoneSubNet() )
{
item_to_merge->SetZoneSubNet( subnet );
}
}
} // End if ( old_subnet > 0 )
} // End if( connected )
}
// End test candidates for the current filled area
indexstart = indexend + 1; // prepare test next area, starting at indexend+1
// (if exists). End read one area in
// zone->m_FilledPolysList
}
} // End read all segments in zone
} // End read all zones candidates
}
