/* ---------------------------------------------------------------------------
* Compute cost function.
* note that area overlap cost is correct for SMD devices: SMD devices on
* opposite sides of the board don't overlap.
*
* Algorithms follow those described in sections 4.1 of
* "Placement and Routing of Electronic Modules" edited by Michael Pecht
* Marcel Dekker, Inc. 1993. ISBN: 0-8247-8916-4 TK7868.P7.P57 1993
*/
static double
ComputeCost (NetListTypePtr Nets, double T0, double T)
{
double W = 0; /* wire cost */
double delta1 = 0; /* wire congestion penalty function */
double delta2 = 0; /* module overlap penalty function */
double delta3 = 0; /* out of bounds penalty */
double delta4 = 0; /* alignment bonus */
double delta5 = 0; /* total area penalty */
Cardinal i, j;
LocationType minx, maxx, miny, maxy;
bool allpads, allsameside;
Cardinal thegroup;
BoxListType bounds = { 0, 0, NULL }; /* save bounding rectangles here */
BoxListType solderside = { 0, 0, NULL }; /* solder side component bounds */
BoxListType componentside = { 0, 0, NULL }; /* component side bounds */
/* make sure the NetList have the proper updated X and Y coords */
UpdateXY (Nets);
/* wire length term. approximated by half-perimeter of minimum
* rectangle enclosing the net. Note that we penalize vias in
* all-SMD nets by making the rectangle a cube and weighting
* the "layer height" of the net. */
for (i = 0; i < Nets->NetN; i++)
{
NetTypePtr n = &Nets->Net[i];
if (n->ConnectionN < 2)
continue; /* no cost to go nowhere */
minx = maxx = n->Connection[0].X;
miny = maxy = n->Connection[0].Y;
thegroup = n->Connection[0].group;
allpads = (n->Connection[0].type == PAD_TYPE);
allsameside = true;
for (j = 1; j < n->ConnectionN; j++)
{
ConnectionTypePtr c = &(n->Connection[j]);
MAKEMIN (minx, c->X);
MAKEMAX (maxx, c->X);
MAKEMIN (miny, c->Y);
MAKEMAX (maxy, c->Y);
if (c->type != PAD_TYPE)
allpads = false;
if (c->group != thegroup)
allsameside = false;
}
/* save bounding rectangle */
{
BoxTypePtr box = GetBoxMemory (&bounds);
box->X1 = minx;
box->Y1 = miny;
box->X2 = maxx;
box->Y2 = maxy;
}
/* okay, add half-perimeter to cost! */
W += (maxx - minx) / 100 + (maxy - miny) / 100 +
((allpads && !allsameside) ? CostParameter.via_cost : 0);
}
/* now compute penalty function Wc which is proportional to
* amount of overlap and congestion. */
/* delta1 is congestion penalty function */
delta1 = CostParameter.congestion_penalty *
sqrt (fabs (ComputeIntersectionArea (&bounds)));
#if 0
printf ("Wire Congestion Area: %f\n", ComputeIntersectionArea (&bounds));
#endif
/* free bounding rectangles */
FreeBoxListMemory (&bounds);
/* now collect module areas (bounding rect of pins/pads) */
/* two lists for solder side / component side. */
ELEMENT_LOOP (PCB->Data);
{
BoxListTypePtr thisside;
BoxListTypePtr otherside;
BoxTypePtr box;
BoxTypePtr lastbox = NULL;
BDimension thickness;
BDimension clearance;
if (TEST_FLAG (ONSOLDERFLAG, element))
{
thisside = &solderside;
otherside = &componentside;
}
else
{
thisside = &componentside;
otherside = &solderside;
}
box = GetBoxMemory (thisside);
/* protect against elements with no pins/pads */
if (element->PinN == 0 && element->PadN == 0)
continue;
/* initialize box so that it will take the dimensions of
* the first pin/pad */
box->X1 = MAX_COORD;
box->Y1 = MAX_COORD;
box->X2 = -MAX_COORD;
box->Y2 = -MAX_COORD;
PIN_LOOP (element);
{
thickness = pin->Thickness / 2;
clearance = pin->Clearance * 2;
EXPANDRECTXY (box,
pin->X - (thickness + clearance),
pin->Y - (thickness + clearance),
pin->X + (thickness + clearance),
pin->Y + (thickness + clearance))}
END_LOOP;
PAD_LOOP (element);
{
thickness = pad->Thickness / 2;
clearance = pad->Clearance * 2;
EXPANDRECTXY (box,
MIN (pad->Point1.X,
pad->Point2.X) - (thickness +
clearance),
MIN (pad->Point1.Y,
pad->Point2.Y) - (thickness +
clearance),
MAX (pad->Point1.X,
pad->Point2.X) + (thickness +
clearance),
MAX (pad->Point1.Y,
pad->Point2.Y) + (thickness + clearance))}
END_LOOP;
/* add a box for each pin to the "opposite side":
* surface mount components can't sit on top of pins */
if (!CostParameter.fast)
PIN_LOOP (element);
{
box = GetBoxMemory (otherside);
thickness = pin->Thickness / 2;
clearance = pin->Clearance * 2;
/* we ignore clearance here */
/* (otherwise pins don't fit next to each other) */
box->X1 = pin->X - thickness;
box->Y1 = pin->Y - thickness;
box->X2 = pin->X + thickness;
box->Y2 = pin->Y + thickness;
/* speed hack! coalesce with last box if we can */
if (lastbox != NULL &&
((lastbox->X1 == box->X1 &&
lastbox->X2 == box->X2 &&
MIN (abs (lastbox->Y1 - box->Y2),
abs (box->Y1 - lastbox->Y2)) <
clearance) || (lastbox->Y1 == box->Y1
&& lastbox->Y2 == box->Y2
&&
MIN (abs
(lastbox->X1 -
box->X2),
abs (box->X1 - lastbox->X2)) < clearance)))
{
EXPANDRECT (lastbox, box);
otherside->BoxN--;
}
else
lastbox = box;
}
END_LOOP;
/* assess out of bounds penalty */
if (element->VBox.X1 < 0 ||
element->VBox.Y1 < 0 ||
element->VBox.X2 > PCB->MaxWidth || element->VBox.Y2 > PCB->MaxHeight)
delta3 += CostParameter.out_of_bounds_penalty;
}
END_LOOP;
/* compute intersection area of module areas box list */
delta2 = sqrt (fabs (ComputeIntersectionArea (&solderside) +
ComputeIntersectionArea (&componentside))) *
(CostParameter.overlap_penalty_min +
(1 - (T / T0)) * CostParameter.overlap_penalty_max);
#if 0
printf ("Module Overlap Area (solder): %f\n",
ComputeIntersectionArea (&solderside));
printf ("Module Overlap Area (component): %f\n",
ComputeIntersectionArea (&componentside));
#endif
FreeBoxListMemory (&solderside);
FreeBoxListMemory (&componentside);
/* reward pin/pad x/y alignment */
/* score higher if pins/pads belong to same *type* of component */
/* XXX: subkey should be *distance* from thing aligned with, so that
* aligning to something far away isn't profitable */
{
/* create r tree */
PointerListType seboxes = { 0, 0, NULL }
, ceboxes =
{
0, 0, NULL};
struct ebox
{
BoxType box;
ElementTypePtr element;
};
direction_t dir[4] = { NORTH, EAST, SOUTH, WEST };
struct ebox **boxpp, *boxp;
rtree_t *rt_s, *rt_c;
int factor;
ELEMENT_LOOP (PCB->Data);
{
boxpp = (struct ebox **)
GetPointerMemory (TEST_FLAG (ONSOLDERFLAG, element) ?
&seboxes : &ceboxes);
*boxpp = malloc (sizeof (**boxpp));
if (*boxpp == NULL )
{
fprintf (stderr, "malloc() failed in %s\n", __FUNCTION__);
exit (1);
}
(*boxpp)->box = element->VBox;
(*boxpp)->element = element;
}
END_LOOP;
rt_s = r_create_tree ((const BoxType **) seboxes.Ptr, seboxes.PtrN, 1);
rt_c = r_create_tree ((const BoxType **) ceboxes.Ptr, ceboxes.PtrN, 1);
FreePointerListMemory (&seboxes);
FreePointerListMemory (&ceboxes);
/* now, for each element, find its neighbor on all four sides */
delta4 = 0;
for (i = 0; i < 4; i++)
ELEMENT_LOOP (PCB->Data);
{
boxp = (struct ebox *)
r_find_neighbor (TEST_FLAG (ONSOLDERFLAG, element) ?
rt_s : rt_c, &element->VBox, dir[i]);
/* score bounding box alignments */
if (!boxp)
continue;
factor = 1;
if (element->Name[0].TextString &&
boxp->element->Name[0].TextString &&
0 == NSTRCMP (element->Name[0].TextString,
boxp->element->Name[0].TextString))
{
delta4 += CostParameter.matching_neighbor_bonus;
factor++;
}
if (element->Name[0].Direction == boxp->element->Name[0].Direction)
delta4 += factor * CostParameter.oriented_neighbor_bonus;
if (element->VBox.X1 ==
boxp->element->VBox.X1 ||
element->VBox.X1 ==
boxp->element->VBox.X2 ||
element->VBox.X2 ==
boxp->element->VBox.X1 ||
element->VBox.X2 ==
boxp->element->VBox.X2 ||
element->VBox.Y1 ==
boxp->element->VBox.Y1 ||
element->VBox.Y1 ==
boxp->element->VBox.Y2 ||
element->VBox.Y2 ==
boxp->element->VBox.Y1 ||
element->VBox.Y2 == boxp->element->VBox.Y2)
delta4 += factor * CostParameter.aligned_neighbor_bonus;
}
END_LOOP;
/* free k-d tree memory */
r_destroy_tree (&rt_s);
r_destroy_tree (&rt_c);
}
/* penalize total area used by this layout */
{
LocationType minX = MAX_COORD, minY = MAX_COORD;
LocationType maxX = -MAX_COORD, maxY = -MAX_COORD;
ELEMENT_LOOP (PCB->Data);
{
MAKEMIN (minX, element->VBox.X1);
MAKEMIN (minY, element->VBox.Y1);
MAKEMAX (maxX, element->VBox.X2);
MAKEMAX (maxY, element->VBox.Y2);
}
END_LOOP;
if (minX < maxX && minY < maxY)
delta5 = CostParameter.overall_area_penalty *
sqrt ((double) (maxX - minX) * (maxY - minY) * 0.0001);
}
if (T == 5)
{
T = W + delta1 + delta2 + delta3 - delta4 + delta5;
printf ("cost components are %.3f %.3f %.3f %.3f %.3f %.3f\n",
W / T, delta1 / T, delta2 / T, delta3 / T, -delta4 / T,
delta5 / T);
}
/* done! */
return W + (delta1 + delta2 + delta3 - delta4 + delta5);
}
/* ---------------------------------------------------------------------------
* Auto-place selected components.
*/
bool
AutoPlaceSelected (void)
{
NetListTypePtr Nets;
PointerListType Selected = { 0, 0, NULL };
PerturbationType pt;
double C0, T0;
bool changed = false;
/* (initial netlist processing copied from AddAllRats) */
/* the netlist library has the text form
* ProcNetlist fills in the Netlist
* structure the way the final routing
* is supposed to look
*/
Nets = ProcNetlist (&PCB->NetlistLib);
if (!Nets)
{
Message (_("Can't add rat lines because no netlist is loaded.\n"));
goto done;
}
Selected = collectSelectedElements ();
if (Selected.PtrN == 0)
{
Message (_("No elements selected to autoplace.\n"));
goto done;
}
/* simulated annealing */
{ /* compute T0 by doing a random series of moves. */
const int TRIALS = 10;
const double Tx = 3e5, P = 0.95;
double Cs = 0.0;
int i;
C0 = ComputeCost (Nets, Tx, Tx);
for (i = 0; i < TRIALS; i++)
{
pt = createPerturbation (&Selected, 1e6);
doPerturb (&pt, false);
Cs += fabs (ComputeCost (Nets, Tx, Tx) - C0);
doPerturb (&pt, true);
}
T0 = -(Cs / TRIALS) / log (P);
printf ("Initial T: %f\n", T0);
}
/* now anneal in earnest */
{
double T = T0;
long steps = 0;
int good_moves = 0, moves = 0;
const int good_move_cutoff = CostParameter.m * Selected.PtrN;
const int move_cutoff = 2 * good_move_cutoff;
printf ("Starting cost is %.0f\n", ComputeCost (Nets, T0, 5));
C0 = ComputeCost (Nets, T0, T);
while (1)
{
double Cprime;
pt = createPerturbation (&Selected, T);
doPerturb (&pt, false);
Cprime = ComputeCost (Nets, T0, T);
if (Cprime < C0)
{ /* good move! */
C0 = Cprime;
good_moves++;
steps++;
}
else if ((random () / (double) RAND_MAX) <
exp (MIN (MAX (-20, (C0 - Cprime) / T), 20)))
{
/* not good but keep it anyway */
C0 = Cprime;
steps++;
}
else
doPerturb (&pt, true); /* undo last change */
moves++;
/* are we at the end of a stage? */
if (good_moves >= good_move_cutoff || moves >= move_cutoff)
{
printf ("END OF STAGE: COST %.0f\t"
"GOOD_MOVES %d\tMOVES %d\t"
"T: %.1f\n", C0, good_moves, moves, T);
/* is this the end? */
if (T < 5 || good_moves < moves / CostParameter.good_ratio)
break;
/* nope, adjust T and continue */
moves = good_moves = 0;
T *= CostParameter.gamma;
/* cost is T dependent, so recompute */
C0 = ComputeCost (Nets, T0, T);
}
}
changed = (steps > 0);
}
done:
if (changed)
{
DeleteRats (false);
AddAllRats (false, NULL);
ClearAndRedrawOutput ();
}
FreePointerListMemory (&Selected);
return (changed);
}
static bool
CheckShorts (LibraryMenuType *theNet)
{
bool newone, warn = false;
PointerListType *generic = (PointerListType *)calloc (1, sizeof (PointerListType));
/* the first connection was starting point so
* the menu is always non-null
*/
void **menu = GetPointerMemory (generic);
*menu = theNet;
ALLPIN_LOOP (PCB->Data);
{
if (TEST_FLAG (DRCFLAG, pin))
{
warn = true;
if (!pin->Spare)
{
Message (_("Warning! Net \"%s\" is shorted to %s pin %s\n"),
&theNet->Name[2],
UNKNOWN (NAMEONPCB_NAME (element)),
UNKNOWN (pin->Number));
SET_FLAG (WARNFLAG, pin);
continue;
}
newone = true;
POINTER_LOOP (generic);
{
if (*ptr == pin->Spare)
{
newone = false;
break;
}
}
END_LOOP;
if (newone)
{
menu = GetPointerMemory (generic);
*menu = pin->Spare;
Message (_("Warning! Net \"%s\" is shorted to net \"%s\"\n"),
&theNet->Name[2],
&((LibraryMenuType *) (pin->Spare))->Name[2]);
SET_FLAG (WARNFLAG, pin);
}
}
}
ENDALL_LOOP;
ALLPAD_LOOP (PCB->Data);
{
if (TEST_FLAG (DRCFLAG, pad))
{
warn = true;
if (!pad->Spare)
{
Message (_("Warning! Net \"%s\" is shorted to %s pad %s\n"),
&theNet->Name[2],
UNKNOWN (NAMEONPCB_NAME (element)),
UNKNOWN (pad->Number));
SET_FLAG (WARNFLAG, pad);
continue;
}
newone = true;
POINTER_LOOP (generic);
{
if (*ptr == pad->Spare)
{
newone = false;
break;
}
}
END_LOOP;
if (newone)
{
menu = GetPointerMemory (generic);
*menu = pad->Spare;
Message (_("Warning! Net \"%s\" is shorted to net \"%s\"\n"),
&theNet->Name[2],
&((LibraryMenuType *) (pad->Spare))->Name[2]);
SET_FLAG (WARNFLAG, pad);
}
}
}
ENDALL_LOOP;
FreePointerListMemory (generic);
free (generic);
return (warn);
}