void __init arch_init_irq(void)
{
int i;
unsigned int gic_rev;
mips_cpu_irq_init();
if (cpu_has_vint)
set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
if (gcmp_present) {
GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
gic_present = 1;
}
if (gic_present) {
#if defined (CONFIG_MIPS_GIC_IPI)
gic_call_int_base = GIC_IPI_CALL_VPE0;
gic_resched_int_base = GIC_IPI_RESCHED_VPE0;
fill_ipi_map();
#endif
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
printk("MIPS GIC RevID: %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
if (cpu_has_vint) {
pr_info("Setting up vectored interrupts\n");
set_vi_handler(2 + GIC_CPU_INT0, gic_irq_dispatch); // CPU
#if defined (CONFIG_MIPS_GIC_IPI)
set_vi_handler(2 + GIC_CPU_INT1, gic_irq_dispatch); // IPI resched
set_vi_handler(2 + GIC_CPU_INT2, gic_irq_dispatch); // IPI call
#endif
set_vi_handler(2 + GIC_CPU_INT3, gic_irq_dispatch); // FE
set_vi_handler(2 + GIC_CPU_INT4, gic_irq_dispatch); // PCIe
}
#if defined (CONFIG_MIPS_GIC_IPI)
set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2 |
STATUSF_IP4 | STATUSF_IP3);
/* setup ipi interrupts */
for (i = 0; i < nr_cpu_ids; i++) {
arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
}
#else
set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2);
#endif
/* set hardware irq, mapped to GIC shared (skip 0, 1, 2, 5, 7) */
for (i = 3; i <= 31; i++) {
if (i != 5 && i != 7)
irq_set_handler(MIPS_GIC_IRQ_BASE + i, handle_level_irq);
}
} else {
unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
{
return GIC_RESCHED_INT(cpu);
}
void __init arch_init_irq(void)
{
#if (defined (CONFIG_IRQ_GIC) && defined(CONFIG_MIPS_MT_SMP)) || !defined (CONFIG_IRQ_GIC)
int i;
#endif
/*
* Mask out all interrupt by writing "1" to all bit position in
* the interrupt reset reg.
*/
#if 0
int mips_cp0_cause, mips_cp0_status;
mips_cp0_cause = read_32bit_cp0_register(CP0_CAUSE);
mips_cp0_status = read_32bit_cp0_register(CP0_STATUS);
printk("cause = %x, status = %x\n", mips_cp0_cause, mips_cp0_status);
mips_cp0_status= mips_cp0_status& ~(CAUSEF_IP0|CAUSEF_IP1|CAUSEF_IP2|CAUSEF_IP3|CAUSEF_IP4|CAUSEF_IP5|CAUSEF_IP6|CAUSEF_IP7);
write_32bit_cp0_register(CP0_STATUS, mips_cp0_status);
#endif
mips_cpu_irq_init();
#if defined (CONFIG_IRQ_GIC)
if (gcmp_present) {
GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
gic_present = 1;
}
if (gic_present) {
#if defined(CONFIG_MIPS_MT_SMP)
gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
gic_resched_int_base = gic_call_int_base - NR_CPUS;
fill_ipi_map();
#endif
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
#if defined(CONFIG_MIPS_MT_SMP)
set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2);
/* set up ipi interrupts */
for (i = 0; i < NR_CPUS; i++) {
arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
}
#else
set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2);
#endif
}
irq_set_handler(SURFBOARDINT_PCIE0, handle_level_irq);
irq_set_handler(SURFBOARDINT_PCIE1, handle_level_irq);
irq_set_handler(SURFBOARDINT_PCIE2, handle_level_irq);
irq_set_handler(SURFBOARDINT_FE, handle_level_irq);
irq_set_handler(SURFBOARDINT_USB, handle_level_irq);
irq_set_handler(SURFBOARDINT_SYSCTL, handle_level_irq);
irq_set_handler(SURFBOARDINT_DRAMC, handle_level_irq);
irq_set_handler(SURFBOARDINT_PCM, handle_level_irq);
irq_set_handler(SURFBOARDINT_HSGDMA, handle_level_irq);
irq_set_handler(SURFBOARDINT_GPIO, handle_level_irq);
irq_set_handler(SURFBOARDINT_DMA, handle_level_irq);
irq_set_handler(SURFBOARDINT_NAND, handle_level_irq);
irq_set_handler(SURFBOARDINT_I2S, handle_level_irq);
irq_set_handler(SURFBOARDINT_SPI, handle_level_irq);
irq_set_handler(SURFBOARDINT_SPDIF, handle_level_irq);
irq_set_handler(SURFBOARDINT_CRYPTO, handle_level_irq);
irq_set_handler(SURFBOARDINT_SDXC, handle_level_irq);
irq_set_handler(SURFBOARDINT_PCTRL, handle_level_irq);
irq_set_handler(SURFBOARDINT_ESW, handle_level_irq);
irq_set_handler(SURFBOARDINT_UART_LITE1, handle_level_irq);
irq_set_handler(SURFBOARDINT_UART_LITE2, handle_level_irq);
irq_set_handler(SURFBOARDINT_UART_LITE3, handle_level_irq);
irq_set_handler(SURFBOARDINT_NAND_ECC, handle_level_irq);
irq_set_handler(SURFBOARDINT_I2C, handle_level_irq);
irq_set_handler(SURFBOARDINT_WDG, handle_level_irq);
irq_set_handler(SURFBOARDINT_TIMER0, handle_level_irq);
irq_set_handler(SURFBOARDINT_TIMER1, handle_level_irq);
#else
for (i = 0; i <= SURFBOARDINT_END; i++) {
irq_set_chip_and_handler(i, &surfboard_irq_type, handle_level_irq);
}
/* Enable global interrupt bit */
*(volatile u32 *)(RALINK_INTENA) = M_SURFBOARD_GLOBAL_INT;
/* hua: 7621 uses GIC -> SURFBOARDINT_PCTRL, which is done by code above */
cp0_perfcount_irq = SURFBOARDINT_PC;
set_c0_status(ST0_IM);
#endif // CONFIG_IRQ_GIC //
#ifdef CONFIG_RALINK_GPIO
ralink_gpio_init_irq();
#endif
#ifdef CONFIG_KGDB
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
static int __init
of_gic_init(struct device_node *node,
struct device_node *parent)
{
struct irq_domain *domain;
struct resource gcmp = { 0 }, gic = { 0 };
unsigned int gic_rev;
int i;
if (of_address_to_resource(node, 0, &gic))
panic("Failed to get gic memory range");
if (request_mem_region(gic.start, resource_size(&gic),
gic.name) < 0)
panic("Failed to request gic memory");
if (of_address_to_resource(node, 2, &gcmp))
panic("Failed to get gic memory range");
if (request_mem_region(gcmp.start, resource_size(&gcmp),
gcmp.name) < 0)
panic("Failed to request gcmp memory");
_gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
if (!_gcmp_base)
panic("Failed to remap gcmp memory\n");
if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
panic("Failed to find gcmp core\n");
/* tell the gcmp where to find the gic */
GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
gic_present = 1;
if (cpu_has_vint) {
set_vi_handler(2, gic_irqdispatch);
set_vi_handler(3, gic_irqdispatch);
set_vi_handler(4, gic_irqdispatch);
set_vi_handler(7, vi_timer_irqdispatch);
}
gic_fill_map();
gic_init(gic.start, resource_size(&gic), gic_intr_map,
ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
0, &irq_domain_ops, NULL);
if (!domain)
panic("Failed to add irqdomain");
#if defined(CONFIG_MIPS_MT_SMP)
for (i = 0; i < nr_cpu_ids; i++) {
setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
}
#endif
change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
STATUSF_IP2);
return 0;
}
