Exemplo n.º 1
0
static void __init gic_basic_init(void)
{
    unsigned int i, cpu;

    /* Setup defaults */
    for (i = 0; i < GIC_NUM_INTRS; i++) {
        GIC_SET_POLARITY(i, GIC_POL_POS);
        GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
        GIC_SET_INTR_MASK(i, 0);
    }

    /* Setup specifics */
    for (i = 0; i < _mapsize; i++) {
        cpu = _intrmap[i].cpunum;
        if (cpu == X)
            continue;

        setup_intr(_intrmap[i].intrnum,
                _intrmap[i].cpunum,
                _intrmap[i].pin,
                _intrmap[i].polarity,
                _intrmap[i].trigtype);
        /* Initialise per-cpu Interrupt software masks */
        if (_intrmap[i].ipiflag)
            set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask);
    }

    vpe_local_setup(numvpes);

    for (i = _irqbase; i < (_irqbase + numintrs); i++)
        set_irq_chip(i, &gic_irq_controller);
}
Exemplo n.º 2
0
static unsigned int gic_irq_startup(unsigned int irq)
{
	irq -= _irqbase;
	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
	GIC_SET_INTR_MASK(irq);
	return 0;
}
Exemplo n.º 3
0
static void __init setup_intr(unsigned int intr, unsigned int cpu,
    unsigned int pin, unsigned int polarity, unsigned int trigtype)
{
    /* Setup Intr to Pin mapping */
    if (pin & GIC_MAP_TO_NMI_MSK) {
        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
        /* FIXME: hack to route NMI to all cpu's */
        for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
            GICWRITE(GIC_REG_ADDR(SHARED,
                      GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
                 0xffffffff);
        }
    } else {
        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
             GIC_MAP_TO_PIN_MSK | pin);
        /* Setup Intr to CPU mapping */
        GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
    }

    /* Setup Intr Polarity */
    GIC_SET_POLARITY(intr, polarity);

    /* Setup Intr Trigger Type */
    GIC_SET_TRIGGER(intr, trigtype);

    /* Init Intr Masks */
    GIC_SET_INTR_MASK(intr, 0);
}
Exemplo n.º 4
0
static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
	unsigned int pin, unsigned int polarity, unsigned int trigtype,
	unsigned int flags)
{
	/* Setup Intr to Pin mapping */
	if (pin & GIC_MAP_TO_NMI_MSK) {
		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
		/* FIXME: hack to route NMI to all cpu's */
		for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
			GICWRITE(GIC_REG_ADDR(SHARED,
					  GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
				 0xffffffff);
		}
	} else {
		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
			 GIC_MAP_TO_PIN_MSK | pin);
		/* Setup Intr to CPU mapping */
		GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
	}

	/* Setup Intr Polarity */
	GIC_SET_POLARITY(intr, polarity);

	/* Setup Intr Trigger Type */
	GIC_SET_TRIGGER(intr, trigtype);

	/* Init Intr Masks */
	GIC_CLR_INTR_MASK(intr);
	/* Initialise per-cpu Interrupt software masks */
	if (flags & GIC_FLAG_IPI)
		set_bit(intr, pcpu_masks[cpu].pcpu_mask);
#ifdef CONFIG_RALINK_SOC
	if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
#else
	if (flags & GIC_FLAG_TRANSPARENT)
#endif
		GIC_SET_INTR_MASK(intr);
	if (trigtype == GIC_TRIG_EDGE)
		gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
}
Exemplo n.º 5
0
void gic_finish_irq(struct irq_data *d)
{
        /* Enable interrupts. */
        GIC_SET_INTR_MASK(d->irq - gic_irq_base);
}
Exemplo n.º 6
0
static void gic_unmask_irq(struct irq_data *d)
{
	unsigned int irq = d->irq - _irqbase;
	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
	GIC_SET_INTR_MASK(irq);
}
Exemplo n.º 7
0
void
gic_finish_irq(struct irq_data *d)
{
	GIC_SET_INTR_MASK(d->irq - gic_irq_base);
}
Exemplo n.º 8
0
static void gic_unmask_irq(unsigned int irq)
{
	irq -= _irqbase;
	pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
	GIC_SET_INTR_MASK(irq);
}