void
DualPermedia3Sync(
ScrnInfoPtr pScrn
){
GLINTPtr pGlint = GLINTPTR(pScrn);
CHECKCLIPPING;
while (GLINT_READ_REG(DMACount) != 0);
GLINT_WAIT(3);
GLINT_WRITE_REG(3, BroadcastMask); /* hack! this shouldn't need to be reloaded */
GLINT_WRITE_REG(0x400, FilterMode);
GLINT_WRITE_REG(0, GlintSync);
/* Read 1st PM3 until Sync Tag shows */
ACCESSCHIP1();
do {
while(GLINT_READ_REG(OutFIFOWords) == 0);
} while (GLINT_READ_REG(OutputFIFO) != Sync_tag);
ACCESSCHIP2();
/* Read 2nd PM3 until Sync Tag shows */
do {
while(GLINT_READ_REG(OutFIFOWords) == 0);
} while (GLINT_READ_REG(OutputFIFO) != Sync_tag);
ACCESSCHIP1();
}
void
glintIBMHideCursor()
{
unsigned char tmp, tmp1;
tmp = GLINT_READ_REG(IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(IBMRGB_curs, IBMRGB_INDEX_LOW);
tmp1 = GLINT_READ_REG(IBMRGB_INDEX_DATA) & ~3;
GLINT_SLOW_WRITE_REG(tmp1, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(tmp, IBMRGB_INDEX_LOW);
}
void
Permedia2Sync(ScrnInfoPtr pScrn)
{
GLINTPtr pGlint = GLINTPTR(pScrn);
CHECKCLIPPING;
while (GLINT_READ_REG(DMACount) != 0);
GLINT_WAIT(2);
GLINT_WRITE_REG(0x400, FilterMode);
GLINT_WRITE_REG(0, GlintSync);
do {
while(GLINT_READ_REG(OutFIFOWords) == 0);
} while (GLINT_READ_REG(OutputFIFO) != Sync_tag);
}
int
PM2VDACInit(int clock)
{
int CC = GLINT_READ_REG(ChipConfig);
/*
* set up the RAMDAC in the right mode
*/
GLINT_WRITE_REG(CC & 0xFFFFFFFD, ChipConfig); /* Disable VGA */
glintOutPM2IndReg(PM2VDACRDMiscControl, 0x00, 0x01); /* 8bit DAC */
switch (glintInfoRec.bitsPerPixel)
{
case 8:
glintOutPM2IndReg(PM2VDACRDPixelSize,0x00,0x00);
glintOutPM2IndReg(PM2VDACRDColorFormat,0x00,0x0E);
break;
case 15:
glintOutPM2IndReg(PM2VDACRDPixelSize,0x00,0x01);
glintOutPM2IndReg(PM2VDACRDColorFormat,0x00,0x61);
break;
case 16:
glintOutPM2IndReg(PM2VDACRDPixelSize,0x00,0x01);
glintOutPM2IndReg(PM2VDACRDColorFormat,0x00,0x70);
break;
case 24:
glintOutPM2IndReg(PM2VDACRDPixelSize,0x00,0x04);
glintOutPM2IndReg(PM2VDACRDColorFormat,0x00,0x20);
break;
case 32:
glintOutPM2IndReg(PM2VDACRDPixelSize,0x00,0x02);
glintOutPM2IndReg(PM2VDACRDColorFormat,0x00,0x20);
break;
}
PM2VDACGlintSetClock(clock);
}
void
glintIBMShowCursor()
{
unsigned char tmp;
/* Enable cursor - X11 mode */
tmp = GLINT_READ_REG(IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(IBMRGB_curs, IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(0x27, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(tmp, IBMRGB_INDEX_LOW);
}
void
glintIBMSetCursorPosition(x, y, xorigin, yorigin)
{
unsigned char tmp;
tmp = GLINT_READ_REG(IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(IBMRGB_curs_hot_x, IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(xorigin & 0xFF, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(IBMRGB_curs_hot_y, IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(yorigin & 0xFF, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(IBMRGB_curs_xl, IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(x & 0xFF, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(IBMRGB_curs_xh, IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG((x >> 8) & 0x0F, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(IBMRGB_curs_yl, IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG(y & 0xFF, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(IBMRGB_curs_yh, IBMRGB_INDEX_LOW);
GLINT_SLOW_WRITE_REG((y >> 8) & 0x0F, IBMRGB_INDEX_DATA);
GLINT_SLOW_WRITE_REG(tmp, IBMRGB_INDEX_LOW);
}
static int saveregs(unsigned char regs[])
{
int i;
unsigned int *p = (unsigned int *)(regs+VGA_TOTAL_REGS);
unsigned char *q = regs+188;
unlock();
p[0]=GLINT_READ_REG(Aperture0);
p[1]=GLINT_READ_REG(Aperture1);
p[2]=GLINT_READ_REG(PMFramebufferWriteMask);
p[3]=GLINT_READ_REG(PMBypassWriteMask);
p[4]=GLINT_READ_REG(DFIFODis);
p[5]=GLINT_READ_REG(FIFODis);
p[6]=GLINT_READ_REG(PMMemConfig);
p[7]=GLINT_READ_REG(PMHTotal);
p[8]=GLINT_READ_REG(PMHbEnd);
p[9]=GLINT_READ_REG(PMHgEnd);
p[10]=GLINT_READ_REG(PMScreenStride);
p[24]=GLINT_READ_REG(PMHsStart);
p[11]=GLINT_READ_REG(PMHsEnd);
p[12]=GLINT_READ_REG(PMVTotal);
p[13]=GLINT_READ_REG(PMVbEnd);
p[14]=GLINT_READ_REG(PMVsStart);
p[15]=GLINT_READ_REG(PMVsEnd);
p[16]=GLINT_READ_REG(PMScreenBase);
p[17]=GLINT_READ_REG(PMVideoControl);
p[18]=GLINT_READ_REG(VClkCtl);
p[19]=GLINT_READ_REG(ChipConfig);
for(i=0;i<768;i++) {
Permedia2ReadAddress(i);
regs[128+VGA_TOTAL_REGS+i]=Permedia2ReadData();
}
switch(chiptype) {
case cPM2:
p[25]=Permedia2InIndReg(PM2DACIndexMCR);
p[26]=Permedia2InIndReg(PM2DACIndexMDCR);
p[27]=Permedia2InIndReg(PM2DACIndexCMR);
p[20]=Permedia2InIndReg(PM2DACIndexClockAM);
p[21]=Permedia2InIndReg(PM2DACIndexClockAN);
p[22]=Permedia2InIndReg(PM2DACIndexClockAP);
break;
case cPM2V:
p[23]=GLINT_READ_REG(PM2VDACRDIndexControl);
p[25]=Permedia2vInIndReg(PM2VDACRDOverlayKey);
p[26]=Permedia2vInIndReg(PM2VDACRDSyncControl);
p[27]=Permedia2vInIndReg(PM2VDACRDMiscControl);
p[28]=Permedia2vInIndReg(PM2VDACRDDACControl);
p[29]=Permedia2vInIndReg(PM2VDACRDPixelSize);
p[30]=Permedia2vInIndReg(PM2VDACRDColorFormat);
p[20]=Permedia2vInIndReg(PM2VDACRDDClk0PreScale);
p[21]=Permedia2vInIndReg(PM2VDACRDDClk0FeedbackScale);
p[22]=Permedia2vInIndReg(PM2VDACRDDClk0PostScale);
for(i=0;i<6;i++)
q[i]=Permedia2vInIndReg(PM2VDACRDCursorPalette+i);
q[6]=Permedia2vInIndReg(PM2VDACRDCursorHotSpotX);
q[7]=Permedia2vInIndReg(PM2VDACRDCursorHotSpotY);
q[8]=Permedia2vInIndReg(PM2VDACRDCursorXLow);
q[9]=Permedia2vInIndReg(PM2VDACRDCursorXHigh);
q[10]=Permedia2vInIndReg(PM2VDACRDCursorYLow);
q[11]=Permedia2vInIndReg(PM2VDACRDCursorYHigh);
q[12]=Permedia2vInIndReg(PM2DACCursorControl);
q[13]=Permedia2vInIndReg(PM2VDACRDCursorMode);
break;
}
return TOTAL_REGS - VGA_TOTAL_REGS;
}
/* Local, called by setmode(). */
static void initializemode(unsigned char *moderegs,
ModeTiming * modetiming, ModeInfo * modeinfo, int mode)
{ /* long k; */
unsigned int *p = (unsigned int *)(moderegs+VGA_TOTAL_REGS);
int t1, t2, t3, t4;
unsigned char m, n, r;
p[0]=0;
p[1]=0;
p[2]=0xffffffff;
p[3]=0xffffffff;
p[4]=1;
p[5]=1;
if(0) p[6]=GLINT_READ_REG(PMMemConfig) | (1<<21);
t1 = modetiming->CrtcHSyncStart - modetiming->CrtcHDisplay;
t2 = modetiming->CrtcVSyncStart - modetiming->CrtcVDisplay;
t3 = modetiming->CrtcHSyncEnd - modetiming->CrtcHSyncStart;
t4 = modetiming->CrtcVSyncEnd - modetiming->CrtcVSyncStart;
switch(modeinfo->bytesPerPixel) {
case 1:
p[7]=modetiming->CrtcHTotal >> 2;
p[11]=(t1+t3) >> 2;
p[24]=t1 >> 2;
p[8]=(modetiming->CrtcHTotal-modetiming->CrtcHDisplay) >>2;
p[10]=modeinfo->lineWidth >> 3;
break;
case 2:
p[7]=modetiming->CrtcHTotal >> 1;
p[11]=(t1+t3) >> 1;
p[24]=t1 >> 1;
p[8]=(modetiming->CrtcHTotal-modetiming->CrtcHDisplay) >>1;
p[10]=modeinfo->lineWidth >> 3;
break;
case 3:
p[7]=(3*modetiming->CrtcHTotal) >> 2;
p[11]=(3*(t1+t3)) >> 2;
p[24]=(3*t1) >> 2;
p[8]=(3*(modetiming->CrtcHTotal-modetiming->CrtcHDisplay)) >> 2;
p[10]=modeinfo->lineWidth >> 3;
break;
case 4:
p[7]=modetiming->CrtcHTotal >> 0;
p[11]=(t1+t3) >> 0;
p[24]=t1 >> 0;
p[8]=(modetiming->CrtcHTotal-modetiming->CrtcHDisplay) >>0;
p[10]=modeinfo->lineWidth >> 3;
break;
}
p[12]= modetiming->CrtcVTotal;
p[15]= t2+t4;
p[14]= t2;
p[13]= modetiming->CrtcVTotal-modetiming->CrtcVDisplay;
p[17]=(1<<5)|(1<<3)|1;
if (modetiming->flags & DOUBLESCAN) {
p[17] |= (1<<2);
}
if((modeinfo->bytesPerPixel>1)||(chiptype==cPM2V)) {
p[17]|= 1<<16;
p[7]>>=1;
p[11]>>=1;
p[24]>>=1;
p[8]>>=1;
}
p[17]=(1<<5)|(1<<3)|1;
if (modetiming->flags & DOUBLESCAN) {
p[17] |= (1<<2);
}
if((modeinfo->bytesPerPixel>1)||(chiptype==cPM2V)) {
p[17]|= 1<<16;
p[7]>>=1;
p[11]>>=1;
p[24]>>=1;
p[8]>>=1;
}
p[18]=GLINT_READ_REG(VClkCtl)&0xfffffffc;
p[16]=0;
p[7] -= 1;
p[12] -= 1;
p[24] -= 1;
p[19]=GLINT_READ_REG(ChipConfig)&0xffffffdd;
switch(chiptype) {
case cPM2:
PM2DAC_CalculateMNPCForClock(modetiming->pixelClock, 14318, &m, &n, &r);
p[20]=m;
p[21]=n;
p[22]=r|8;
break;
case cPM2V:
if(modetiming->pixelClock>28635) {
int
Permedia3MemorySizeDetect(ScrnInfoPtr pScrn)
{
GLINTPtr pGlint = GLINTPTR (pScrn);
CARD32 size = 0, temp, temp1, temp2, i;
/* We can map 64MB, as that's the size of the Permedia3 aperture
* regardless of memory configuration */
pGlint->FbMapSize = 64*1024*1024;
#ifndef XSERVER_LIBPCIACCESS
/* Mark as VIDMEM_MMIO to avoid write-combining while detecting memory */
pGlint->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_MMIO,
pGlint->PciTag, pGlint->FbAddress, pGlint->FbMapSize);
#else
{
void** result = (void**)&pGlint->FbBase;
int err = pci_device_map_range(pGlint->PciInfo,
pGlint->FbAddress,
pGlint->FbMapSize,
PCI_DEV_MAP_FLAG_WRITABLE,
result);
if (err)
return FALSE;
}
#endif
if (pGlint->FbBase == NULL)
return 0;
temp = GLINT_READ_REG(PM3MemBypassWriteMask);
GLINT_SLOW_WRITE_REG(0xffffffff, PM3MemBypassWriteMask);
/* The Permedia3 splits up memory, and even replicates it. Grrr.
* So that each 32MB appears at offset 0, and offset 32, unless
* there's really 64MB attached to the chip.
* So, 16MB appears at offset 0, nothing between 16-32, then it re-appears
* at offset 32.
* This below is to detect the cases of memory combinations
*/
/* Test first 32MB */
for(i=0;i<32;i++) {
/* write test pattern */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, i*0x00345678);
mem_barrier();
temp1 = MMIO_IN32(pGlint->FbBase, i*1024*1024);
/* Let's check for wrapover, write will fail at 16MB boundary */
if (temp1 == (i*0x00345678))
size = i;
else
break;
}
/* Ok, we're satisfied we've got 32MB, let's test the second lot */
if ((size + 1) == i) {
for(i=0;i<32;i++) {
/* Clear first 32MB */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, 0);
}
mem_barrier();
for(i=32;i<64;i++) {
/* write test pattern */
MMIO_OUT32(pGlint->FbBase, i*1024*1024, i*0x00345678);
mem_barrier();
temp1 = MMIO_IN32(pGlint->FbBase, i*1024*1024);
temp2 = MMIO_IN32(pGlint->FbBase, (i-32)*1024*1024);
/* Let's check for wrapover */
if ( (temp1 == (i*0x00345678)) && (temp2 == 0) )
size = i;
else
break;
}
}
GLINT_SLOW_WRITE_REG(temp, PM3MemBypassWriteMask);
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(pScrn->scrnIndex, (pointer)pGlint->FbBase,
pGlint->FbMapSize);
#else
pci_device_unmap_range(pGlint->PciInfo, pGlint->FbBase, pGlint->FbMapSize);
#endif
pGlint->FbBase = NULL;
pGlint->FbMapSize = 0;
return ( (size+1) * 1024 );
}
Bool
Permedia3Init(ScrnInfoPtr pScrn, DisplayModePtr mode, GLINTRegPtr pReg)
{
GLINTPtr pGlint = GLINTPTR(pScrn);
CARD32 temp1, temp2, temp3, temp4;
if ((pGlint->numMultiDevices == 2) || (IS_J2000)) {
STOREREG(GCSRAperture, GCSRSecondaryGLINTMapEn);
}
if (pGlint->MultiAperture) {
STOREREG(GMultGLINTAperture, pGlint->realWidth);
STOREREG(GMultGLINT1, PCI_REGION_BASE(pGlint->MultiPciInfo[0], 2, REGION_MEM) & 0xFF800000);
STOREREG(GMultGLINT2, PCI_REGION_BASE(pGlint->MultiPciInfo[1], 2, REGION_MEM) & 0xFF800000);
}
STOREREG(PM3MemBypassWriteMask, 0xffffffff);
STOREREG(Aperture0, 0x00000000);
STOREREG(Aperture1, 0x00000000);
if (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA)
STOREREG(DFIFODis, 0x00000001);
STOREREG(FIFODis, 0x00000007);
temp1 = mode->CrtcHSyncStart - mode->CrtcHDisplay;
temp2 = mode->CrtcVSyncStart - mode->CrtcVDisplay;
temp3 = mode->CrtcHSyncEnd - mode->CrtcHSyncStart;
temp4 = mode->CrtcVSyncEnd - mode->CrtcVSyncStart;
STOREREG(PMHTotal, Shiftbpp(pScrn, mode->CrtcHTotal) - 1);
STOREREG(PMHsEnd, Shiftbpp(pScrn, temp1 + temp3));
STOREREG(PMHsStart, Shiftbpp(pScrn, temp1));
STOREREG(PMHbEnd, Shiftbpp(pScrn, mode->CrtcHTotal - mode->CrtcHDisplay));
STOREREG(PMHgEnd, Shiftbpp(pScrn, mode->CrtcHTotal - mode->CrtcHDisplay));
STOREREG(PMScreenStride, Shiftbpp(pScrn, pScrn->displayWidth));
STOREREG(PMVTotal, mode->CrtcVTotal - 1);
STOREREG(PMVsEnd, temp2 + temp4 - 1);
STOREREG(PMVsStart, temp2 - 1);
STOREREG(PMVbEnd, mode->CrtcVTotal - mode->CrtcVDisplay);
switch (pScrn->bitsPerPixel)
{
case 8:
STOREREG(PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_8BIT);
STOREREG(PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_8BIT);
STOREREG(PMVideoControl, 1 | (1 << 3) | (1 << 5) | (0 << 19));
break;
case 16:
#if X_BYTE_ORDER != X_BIG_ENDIAN
STOREREG(PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_16BIT);
STOREREG(PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_16BIT);
#else
STOREREG(PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_16BIT |
PM3ByApertureMode_BYTESWAP_BADC);
STOREREG(PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_16BIT |
PM3ByApertureMode_BYTESWAP_BADC);
#endif
STOREREG(PMVideoControl, 1 | (1 << 3) | (1 << 5) | (1 << 19));
break;
case 32:
#if X_BYTE_ORDER != X_BIG_ENDIAN
STOREREG(PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_32BIT);
STOREREG(PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_32BIT);
#else
STOREREG(PM3ByAperture1Mode, PM3ByApertureMode_PIXELSIZE_32BIT |
PM3ByApertureMode_BYTESWAP_DCBA);
STOREREG(PM3ByAperture2Mode, PM3ByApertureMode_PIXELSIZE_32BIT |
PM3ByApertureMode_BYTESWAP_DCBA);
#endif
STOREREG(PMVideoControl, 1 | (1 << 3) | (1 << 5) | (2 << 19));
break;
}
STOREREG(VClkCtl, GLINT_READ_REG(VClkCtl) & 0xFFFFFFFC);
STOREREG(PMScreenBase, 0x00000000);
STOREREG(ChipConfig, GLINT_READ_REG(ChipConfig) & 0xFFFFFFFD);
{
/* Get the programmable clock values */
unsigned char m,n,p;
/* Let's program the dot clock */
switch (pGlint->Chipset) {
case PCI_VENDOR_3DLABS_CHIP_PERMEDIA4:
case PCI_VENDOR_3DLABS_CHIP_R4:
(void) PM4DAC_CalculateClock(mode->Clock, pGlint->RefClock, &m,&n,&p);
break;
case PCI_VENDOR_3DLABS_CHIP_PERMEDIA3:
(void) PM3DAC_CalculateClock(mode->Clock, pGlint->RefClock, &m,&n,&p);
break;
case PCI_VENDOR_3DLABS_CHIP_GAMMA:
switch (pGlint->MultiChip) {
case PCI_CHIP_3DLABS_PERMEDIA3:
(void) PM3DAC_CalculateClock(mode->Clock,
pGlint->RefClock, &m,&n,&p);
break;
case PCI_CHIP_3DLABS_R4:
(void) PM4DAC_CalculateClock(mode->Clock,
pGlint->RefClock, &m,&n,&p);
break;
}
break;
}
STOREDAC(PM3RD_DClk0PreScale, m);
STOREDAC(PM3RD_DClk0FeedbackScale, n);
STOREDAC(PM3RD_DClk0PostScale, p);
}
temp1 = 0;
temp2 = 0;
temp3 = 0;
if (pGlint->UseFlatPanel) {
temp2 |= PM3RD_DACControl_BLANK_PEDESTAL_ENABLE;
temp3 |= PM3RD_MiscControl_VSB_OUTPUT_ENABLE;
STOREREG(VSConfiguration, 0x06);
STOREREG(VSBBase, 1<<14);
}
if (mode->Flags & V_PHSYNC) temp1 |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
if (mode->Flags & V_PVSYNC) temp1 |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
STOREREG(PM2VDACRDIndexControl, 0x00);
STOREDAC(PM2VDACRDSyncControl, temp1);
STOREDAC(PM2VDACRDDACControl, temp2);
if (pScrn->rgbBits == 8)
temp3 |= 0x01; /* 8bit DAC */
switch (pScrn->bitsPerPixel)
{
case 8:
STOREDAC(PM2VDACRDPixelSize, 0x00);
STOREDAC(PM2VDACRDColorFormat, 0x2E);
break;
case 16:
temp3 |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE;
STOREDAC(PM2VDACRDPixelSize, 0x01);
if (pScrn->depth == 15) {
STOREDAC(PM2VDACRDColorFormat, 0x61);
} else {
STOREDAC(PM2VDACRDColorFormat, 0x70);
}
break;
case 24:
temp3 |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE;
STOREDAC(PM2VDACRDPixelSize, 0x04);
STOREDAC(PM2VDACRDColorFormat, 0x20);
break;
case 32:
temp3 |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE;
if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
temp3 |= 0x18;
STOREDAC(PM2VDACRDOverlayKey, pScrn->colorKey);
}
STOREDAC(PM2VDACRDPixelSize, 0x02);
STOREDAC(PM2VDACRDColorFormat, 0x20);
break;
}
STOREDAC(PM2VDACRDMiscControl, temp3);
STOREREG(PM3FifoControl, 0x905); /* Lower the default fifo threshold */
return(TRUE);
}
void
Permedia3PreInit(ScrnInfoPtr pScrn)
{
GLINTPtr pGlint = GLINTPTR(pScrn);
CARD32 LocalMemCaps;
TRACE_ENTER("Permedia3PreInit");
if (IS_J2000) {
unsigned char m,n,p;
if (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA)
GLINT_SLOW_WRITE_REG(GCSRSecondaryGLINTMapEn, GCSRAperture);
/* Memory timings for the Appian J2000 board.
* This is needed for the second head which is left un-initialized
* by the bios, thus freezing the machine. */
GLINT_SLOW_WRITE_REG(0x02e311B8, PM3LocalMemCaps);
GLINT_SLOW_WRITE_REG(0x07424905, PM3LocalMemTimings);
GLINT_SLOW_WRITE_REG(0x0c000003, PM3LocalMemControl);
GLINT_SLOW_WRITE_REG(0x00000061, PM3LocalMemRefresh);
GLINT_SLOW_WRITE_REG(0x00000000, PM3LocalMemPowerDown);
/* Let's program the K, M and S Clocks to the same values as the bios
* does for first head :
* - KClk and MClk are 105Mhz.
* - S Clock is set to PClk.
* Note 1 : pGlint->RefClock is not set yet, so use 14318 instead.
* Note 2 : KClk gets internally halved, so we need to double it.
*/
(void) PM3DAC_CalculateClock(2*105000, 14318, &m,&n,&p);
Permedia2vOutIndReg(pScrn, PM3RD_KClkPreScale, 0x00, m);
Permedia2vOutIndReg(pScrn, PM3RD_KClkFeedbackScale, 0x00, n);
Permedia2vOutIndReg(pScrn, PM3RD_KClkPostScale, 0x00, p);
Permedia2vOutIndReg(pScrn, PM3RD_KClkControl, 0x00,
PM3RD_KClkControl_STATE_RUN |
PM3RD_KClkControl_SOURCE_PLL |
PM3RD_KClkControl_ENABLE);
Permedia2vOutIndReg(pScrn, PM3RD_MClkControl, 0x00,
PM3RD_MClkControl_STATE_RUN |
PM3RD_MClkControl_SOURCE_KCLK |
PM3RD_MClkControl_ENABLE);
Permedia2vOutIndReg(pScrn, PM3RD_SClkControl, 0x00,
PM3RD_SClkControl_STATE_RUN |
PM3RD_SClkControl_SOURCE_PCLK |
PM3RD_SClkControl_ENABLE);
}
#if defined(__alpha__)
/*
* On Alpha, we have to "int10" secondary VX1 cards early;
* otherwise, some information taken from registers, like
* memory size, is incorrect.
*/
if (!xf86IsPrimaryPci(pGlint->PciInfo)) {
if ( IS_QVX1 ) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"VX1 secondary enabling VGA before int10\n");
/* Enable VGA on the current card. */
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xf8);
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xf4);
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xfc);
/* The card we are on should be VGA-enabled now, so run int10. */
if (xf86LoadSubModule(pScrn, "int10")) {
xf86Int10InfoPtr pInt;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Initializing int10\n");
pInt = xf86InitInt10(pGlint->pEnt->index);
xf86FreeInt10(pInt);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"VX1 secondary disabling VGA after int10\n");
/* Finally, disable VGA on the current card. */
PCI_WRITE_BYTE(pGlint->PciInfo, 0x70, 0xf8);
PCI_WRITE_BYTE(pGlint->PciInfo, 0x01, 0xf4);
PCI_WRITE_BYTE(pGlint->PciInfo, 0x00, 0xfc);
}
}
#endif /* __alpha__ */
/* If we have SDRAM instead of SGRAM, we have to do some things
differently in the FillRectSolid code. */
LocalMemCaps = GLINT_READ_REG(PM3LocalMemCaps);
pGlint->PM3_UsingSGRAM = !(LocalMemCaps & PM3LocalMemCaps_NoWriteMask);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using %s memory\n",
pGlint->PM3_UsingSGRAM ? "SGRAM" : "SDRAM");
TRACE_EXIT("Permedia3PreInit");
}