Exemplo n.º 1
0
/*********************************************************************//**
 * @brief		GPDMA interrupt handler sub-routine
 * @param[in]	None
 * @return 		None
 **********************************************************************/
void DMA_IRQHandler (void)
{
	// check GPDMA interrupt on channel 0
	if (GPDMA_IntGetStatus(GPDMA_STAT_INT, 0)){ //check interrupt status on channel 0
		// Check counter terminal status
		if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, 0)){
			// Clear terminate counter Interrupt pending
			GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, 0);
				Channel0_TC++;
		}
		if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, 0)){
			// Clear error counter Interrupt pending
			GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, 0);
			Channel0_Err++;
		}
	}
}
Exemplo n.º 2
0
/*********************************************************************//**
 * @brief		GPDMA interrupt handler sub-routine
 * @param[in]	None
 * @return 		None
 **********************************************************************/
void DMA_IRQHandler (void)
{
	uint32_t tmp;
		// Scan interrupt pending
	for (tmp = 0; tmp <= 7; tmp++) {
		if (GPDMA_IntGetStatus(GPDMA_STAT_INT, tmp)){
			// Check counter terminal status
			if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, tmp)){
				// Clear terminate counter Interrupt pending
				GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, tmp);

				switch (tmp){
					case 0:
						Channel0_TC++;
						GPDMA_ChannelCmd(0, DISABLE);
						break;
					case 1:
						Channel1_TC++;
						GPDMA_ChannelCmd(1, DISABLE);
						break;
					default:
						break;
				}

			}
				// Check error terminal status
			if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, tmp)){
				// Clear error counter Interrupt pending
				GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, tmp);
				switch (tmp){
					case 0:
						Channel0_Err++;
						GPDMA_ChannelCmd(0, DISABLE);
						break;
					case 1:
						Channel1_Err++;
						GPDMA_ChannelCmd(1, DISABLE);
						break;
					default:
						break;
				}
			}
		}
	}
}
Exemplo n.º 3
0
void hw_spi_dma_counter (uint8_t channel) {
    // Check counter terminal IR
    if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, channel)) {
        // Clear terminate counter Interrupt pending
        GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, channel);
        // This interrupt status should be hit for both tx and rx
        uint8_t done_count = ((spi_async_status.txbuf != NULL) && (spi_async_status.rxbuf != NULL)) ? 2 : 1;
        if (++spi_async_status.transferCount == done_count) {
            // Trigger the callback
            (*spi_async_status.callback)();
        }
    }
    if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, channel)) {
        // Clear error counter Interrupt pending
        GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, channel);
        // Register the error in our struct
        spi_async_status.transferError++;
        // Trigger the callback because there was an error
        (*spi_async_status.callback)();
    }
}
Exemplo n.º 4
0
//Interrupt that is triggered when the the DMA is finished
void DMA_IRQHandler(void) {
	//Check which channel triggered the interrupt

	//Transmit
	if (GPDMA_IntGetStatus(GPDMA_STAT_INT, 0) == SET) {
		if (GPDMA_IntGetStatus(GPDMA_STAT_INTTC, 0) == SET) {
			//Clear interrupt flag
			GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, 0);

			//Set transit ready flag
			txReady = 1;

			//If both transmit and receive are finished
			if (txReady && rxReady) {
				//Clear flags
				txReady = 0;
				rxReady = 0;
				//Restart DMA
				initI2SDMA((uint32_t) txActive, (uint32_t) rxActive);

				//Set flag for processing in main loop
				needsProcessing = 1;
			}
		}
		if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, 0) == SET) {
			GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, 0);
		}
	}
	//Receive
	if (GPDMA_IntGetStatus(GPDMA_STAT_INT, 1) == SET) {
		if (GPDMA_IntGetStatus(GPDMA_STAT_INTTC, 1) == SET) {
			GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, 1);

			//Set receive flag
			rxReady = 1;

			//If both transmit and receive are finished
			if (txReady && rxReady) {
				//Clear flags
				txReady = 0;
				rxReady = 0;
				//Restart DMA
				initI2SDMA((uint32_t) txActive, (uint32_t) rxActive);

				//Set flag for processing in main loop
				needsProcessing = 1;
			}
		}
		if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, 1) == SET) {
			GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, 1);
		}
	}

}
Exemplo n.º 5
0
void DMA_IRQHandler (void){
//	xprintf("DMA_IRQ");
//	ticks_at_DMA_start = ticks;
	// check GPDMA interrupt on channel 0
	if (GPDMA_IntGetStatus(GPDMA_STAT_INT, 0)){
		// Check counter terminal status
		if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, 0)){
			// Clear terminate counter Interrupt pending
			GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, 0);
//			ticks_after_DMA_finish = ticks;
			TIM_Cmd(LPC_TIM1,ENABLE);
		}
		// Check error terminal status
		if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, 0)){
			// Clear error counter Interrupt pending
			GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, 0);
		}
	}
#ifdef RxDMA
	// check GPDMA interrupt on channel 1
	if (GPDMA_IntGetStatus(GPDMA_STAT_INT, 1)){
		// Check counter terminal status
		if(GPDMA_IntGetStatus(GPDMA_STAT_INTTC, 1)){
			// Clear terminate counter Interrupt pending
			GPDMA_ClearIntPending (GPDMA_STATCLR_INTTC, 1);
				Channel1_TC++;
//				xprintf("ch1_TC:%d\n",Channel0_TC);
		}
		// Check error terminal status
		if (GPDMA_IntGetStatus(GPDMA_STAT_INTERR, 1)){
			// Clear error counter Interrupt pending
			GPDMA_ClearIntPending (GPDMA_STATCLR_INTERR, 1);
			Channel1_Err++;
//			xprintf("ch1_Err:%d\n",Channel0_Err);
		}
	}
	xprintf("Rx:0x%x ",LED_PRECALC1[0][0]);
#endif
}