static int qrd_gpios_request_enable(const struct msm_gpio *table, int size)
{
int i;
const struct msm_gpio *g;
struct gpiomux_setting setting;
int rc = msm_gpios_request(table, size);
if (!rc){
for (i = 0; i < size; i++) {
g = table + i;
/* use msm_gpiomux_write which can save old configuration */
setting.func = GPIO_FUNC(g->gpio_cfg);
setting.dir = GPIO_DIR(g->gpio_cfg);
setting.pull = GPIO_PULL(g->gpio_cfg);
setting.drv = GPIO_DRVSTR(g->gpio_cfg);
msm_gpiomux_write(GPIO_PIN(g->gpio_cfg), GPIOMUX_ACTIVE, &setting, NULL);
pr_debug("I2C pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
}
}
return rc;
}
static void exynos_pinmux_i2c(int start, int func)
{
gpio_cfg_pin(start, GPIO_FUNC(func));
gpio_cfg_pin(start + 1, GPIO_FUNC(func));
gpio_set_pull(start, GPIO_PULL_NONE);
gpio_set_pull(start + 1, GPIO_PULL_NONE);
}
void exynos_pinmux_spi4(void)
{
int i;
for (i = 0; i < 2; i++) {
gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4));
gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4));
}
}
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
int i, start = 0, gpio_func = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
start = 0;
gpio_func = GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
bank = &gpio1->c2;
bank_ext = NULL;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio1->c3;
bank_ext = &gpio1->c4;
start = 3;
gpio_func = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
bank = &gpio1->c4;
bank_ext = NULL;
break;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
}
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
return 0;
}
int board_mmc_init(bd_t *bis)
{
int i, err;
/*
* MMC2 SD card GPIO:
*
* GPK2[0] SD_2_CLK(2)
* GPK2[1] SD_2_CMD(2)
* GPK2[2] SD_2_CDn
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
if (i == 0 || i == 1) {
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;
}
static int tlmm_dump_cfg(char* buf,unsigned gpio, unsigned cfg, int output_val)
{
static char* drvstr_str[] = { "2", "4", "6", "8", "10", "12", "14", "16" }; // mA
static char* pull_str[] = { "N", "D", "K", "U" }; // "NO_PULL", "PULL_DOWN", "KEEPER", "PULL_UP"
static char* dir_str[] = { "I", "O" }; // "Input", "Output"
char func_str[20];
char* p = buf;
int drvstr = GPIO_DRVSTR(cfg);
int pull = GPIO_PULL(cfg);
int dir = GPIO_DIR(cfg);
int func = GPIO_FUNC(cfg);
//printk("%s(), drvstr=%d, pull=%d, dir=%d, func=%d\n", __func__, drvstr, pull, dir, func);
sprintf(func_str, "%d", func);
p += sprintf(p, "%d:0x%x %s%s%s%s", gpio, cfg,
func_str, pull_str[pull], dir_str[dir], drvstr_str[drvstr]);
p += sprintf(p, " = %d", output_val);
p += sprintf(p, "\n");
return p - buf;
}
static void board_uart_init(void)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
int i;
/*
* UART2 GPIOs
* GPA1CON[0] = UART_2_RXD(2)
* GPA1CON[1] = UART_2_TXD(2)
* GPA1CON[2] = I2C_3_SDA (3)
* GPA1CON[3] = I2C_3_SCL (3)
*/
for (i = 0; i < 4; i++) {
s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
}
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio2->y4, 7, 1);
}
static void exynos4_uart_config(int peripheral)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->a0;
start = 4;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
count = 2;
break;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
}
}
void exynos_pinmux_sromc(int bank, int sixteen_bit)
{
int i;
if (bank > 3) {
printk(BIOS_DEBUG, "Unsupported sromc bank %d.\n", bank);
return;
}
gpio_cfg_pin(GPIO_Y00 + bank, GPIO_FUNC(2));
gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2));
gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2));
for (i = 2; i < 4; i++)
gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2));
for (i = 0; i < 8; i++) {
gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2));
gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP);
gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2));
gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP);
if (sixteen_bit) {
gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2));
gpio_set_pull(GPIO_Y60 + i, GPIO_PULL_UP);
}
}
}
static void exynos_pinmux_uart(int start, int count)
{
int i;
for (i = start; i < start + count; i++) {
gpio_set_pull(i, GPIO_PULL_NONE);
gpio_cfg_pin(i, GPIO_FUNC(0x2));
}
}
void exynos_pinmux_i2s1(void)
{
int i;
for (i = 0; i < 5; i++) {
gpio_cfg_pin(GPIO_B00 + i, GPIO_FUNC(0x02));
gpio_set_pull(GPIO_B00 + i, GPIO_PULL_NONE);
}
}
static void exynos5_i2s_config(int peripheral)
{
int i;
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
for (i = 0; i < 5; i++)
s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
}
static void exynos_pinmux_sdmmc(struct gpio *gpios, int num_gpios)
{
int i;
for (i = 0; i < num_gpios; i++) {
gpio_set_drv(gpios[i].pin, gpios[i].drv);
gpio_set_pull(gpios[i].pin, gpios[i].pull);
gpio_cfg_pin(gpios[i].pin, GPIO_FUNC(gpios[i].func));
}
}
static void exynos_pinmux_spi(int start, int cfg)
{
int i;
for (i = 0; i < 4; i++) {
gpio_cfg_pin(start + i, GPIO_FUNC(cfg));
gpio_set_pull(start + i, GPIO_PULL_NONE);
gpio_set_drv(start + i, GPIO_DRV_3X);
}
}
void exynos_pinmux_dphpd(void)
{
/* Set Hotplug detect for DP */
gpio_cfg_pin(GPIO_X07, GPIO_FUNC(0x3));
/*
* Hotplug detect should have an external pullup; disable the
* internal pulldown so they don't fight.
*/
gpio_set_pull(GPIO_X07, GPIO_PULL_NONE);
}
void __gpio_tlmm_config(unsigned config)
{
uint32_t flags;
unsigned gpio = GPIO_PIN(config);
flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
__raw_writel(flags, GPIO_CONFIG(gpio));
}
static void exynos_pinmux_sdmmc(int start, int start_ext)
{
int i;
if (start_ext) {
for (i = 0; i <= 3; i++) {
gpio_cfg_pin(start_ext + i, GPIO_FUNC(0x2));
gpio_set_pull(start_ext + i, GPIO_PULL_UP);
gpio_set_drv(start_ext + i, GPIO_DRV_4X);
}
}
for (i = 0; i < 2; i++) {
gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
gpio_set_pull(start + i, GPIO_PULL_NONE);
gpio_set_drv(start + i, GPIO_DRV_4X);
}
for (i = 2; i <= 6; i++) {
gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
gpio_set_pull(start + i, GPIO_PULL_UP);
gpio_set_drv(start + i, GPIO_DRV_4X);
}
}
void exynos_cfg_lcd_gpio(void)
{
unsigned int i, f3_end = 4;
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
/* pull-up/down disable */
s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
/* drive strength to max (24bit) */
s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
}
for (i = 0; i < f3_end; i++) {
/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
/* pull-up/down disable */
s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
/* drive strength to max (24bit) */
s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
}
/* gpio pad configuration for LCD reset. */
s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
spi_init();
}
int gpio_tlmm_config(unsigned config, unsigned disable)
{
uint32_t flags;
unsigned gpio = GPIO_PIN(config);
if (gpio > NR_MSM_GPIOS)
return -EINVAL;
flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
writel(flags, GPIO_CONFIG(gpio));
return 0;
}
void exynos_cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
/* For Backlight */
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->b2, 0, 1);
/* LCD power on */
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->x1, 5, 1);
/* Set Hotplug detect for DP */
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
}
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
/* gpio configuration GPK0CON */
s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
| SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
| SROMC_BC_PMC(0x0F);
/* Select and configure the SROMC bank */
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
int gpio_tlmm_config(unsigned config, unsigned disable)
{
uint32_t v2flags;
unsigned long irq_flags;
unsigned gpio = GPIO_PIN(config);
if (gpio > NR_MSM_GPIOS)
return -EINVAL;
v2flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
spin_lock_irqsave(&gpio_lock, irq_flags);
writel(v2flags, GPIO_CONFIG(gpio));
spin_unlock_irqrestore(&gpio_lock, irq_flags);
return 0;
}
static int tlmm_get_cfg(unsigned gpio, unsigned* cfg)
{
unsigned flags;
BUG_ON(gpio >= TLMM_NUM_GPIO);
//printk("%s(), gpio=%d, addr=0x%08x\n", __func__, gpio, (unsigned int)GPIO_CONFIG(gpio));
#if 0
flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
((GPIO_FUNC(config) << 2) & (0xf << 2)) |
((GPIO_PULL(config) & 0x3));
#else
flags = __raw_readl(GPIO_CONFIG(gpio));
#endif
*cfg = GPIO_CFG(gpio, (flags >> 2) & 0xf, (flags >> 9) & 0x1, flags & 0x3, (flags >> 6) & 0x7);
return 0;
}
/*
* Miscellaneous platform dependent initialisations
*/
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
struct s5pc100_gpio *const gpio =
(struct s5pc100_gpio *)S5PC100_GPIO_BASE;
/* gpio configuration GPK0CON */
gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
| SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
| SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
/* Select and configure the SROMC bank */
s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
}
void tlmm_before_sleep_set_configs(void)
{
int res;
unsigned i;
//only set tlmms before sleep when it's enabled
if (!before_sleep_table_enabled)
return;
printk("%s(), before_sleep_table_enabled=%d\n", __func__, before_sleep_table_enabled);
for(i = 0; i < TLMM_NUM_GPIO; ++i) {
unsigned cfg;
int gpio;
int dir;
int func;
int output_val = 0;
cfg = before_sleep_table_configs[i];
gpio = GPIO_PIN(cfg);
if(gpio != i)//(cfg & ~0x20000000) == 0 ||
continue;
output_val = HAL_OUTPUT_VAL(cfg);
//Clear the output value
//cfg &= ~0x40000000;
dir = GPIO_DIR(cfg);
func = GPIO_FUNC(cfg);
printk("%s(), [%d]: 0x%x\n", __func__, i, cfg);
res = gpio_tlmm_config((cfg & ~0x40000000), GPIO_CFG_ENABLE);
if(res < 0) {
printk("Error: Config failed.\n");
}
if((func == 0) && (dir == 1)) // gpio output
__msm_gpio_set_inout(i, output_val);
}
}
int msm_gpios_disable(const struct msm_gpio *table, int size)
{
int rc = 0;
int i;
const struct msm_gpio *g;
for (i = size-1; i >= 0; i--) {
int tmp;
g = table + i;
tmp = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_DISABLE);
if (tmp) {
pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_DISABLE)"
" <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
if (!rc)
rc = tmp;
}
}
return rc;
}
int msm_gpios_enable(const struct msm_gpio *table, int size)
{
int rc;
int i;
const struct msm_gpio *g;
for (i = 0; i < size; i++) {
g = table + i;
rc = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_ENABLE);
if (rc) {
pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_ENABLE)"
" <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
goto err;
}
}
return 0;
err:
msm_gpios_disable(table, i);
return rc;
}
void exynos5_spi_config(int peripheral)
{
int cfg = 0, pin = 0, i;
struct s5p_gpio_bank *bank = NULL;
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct exynos5_gpio_part2 *gpio2 =
(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
switch (peripheral) {
case PERIPH_ID_SPI0:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 0;
break;
case PERIPH_ID_SPI1:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 4;
break;
case PERIPH_ID_SPI2:
bank = &gpio1->b1;
cfg = GPIO_FUNC(0x5);
pin = 1;
break;
case PERIPH_ID_SPI3:
bank = &gpio2->f1;
cfg = GPIO_FUNC(0x2);
pin = 0;
break;
case PERIPH_ID_SPI4:
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
}
break;
}
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
s5p_gpio_cfg_pin(bank, i, cfg);
}
}
static void exynos4_i2c_config(int peripheral, int flags)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
break;
}
}
static void exynos5_sromc_config(int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
int i;
/*
* SROM:CS1 and EBI
*
* GPY0[0] SROM_CSn[0]
* GPY0[1] SROM_CSn[1](2)
* GPY0[2] SROM_CSn[2]
* GPY0[3] SROM_CSn[3]
* GPY0[4] EBI_OEn(2)
* GPY0[5] EBI_EEn(2)
*
* GPY1[0] EBI_BEn[0](2)
* GPY1[1] EBI_BEn[1](2)
* GPY1[2] SROM_WAIT(2)
* GPY1[3] EBI_DATA_RDn(2)
*/
s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
for (i = 0; i < 4; i++)
s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
/*
* EBI: 8 Addrss Lines
*
* GPY3[0] EBI_ADDR[0](2)
* GPY3[1] EBI_ADDR[1](2)
* GPY3[2] EBI_ADDR[2](2)
* GPY3[3] EBI_ADDR[3](2)
* GPY3[4] EBI_ADDR[4](2)
* GPY3[5] EBI_ADDR[5](2)
* GPY3[6] EBI_ADDR[6](2)
* GPY3[7] EBI_ADDR[7](2)
*
* EBI: 16 Data Lines
*
* GPY5[0] EBI_DATA[0](2)
* GPY5[1] EBI_DATA[1](2)
* GPY5[2] EBI_DATA[2](2)
* GPY5[3] EBI_DATA[3](2)
* GPY5[4] EBI_DATA[4](2)
* GPY5[5] EBI_DATA[5](2)
* GPY5[6] EBI_DATA[6](2)
* GPY5[7] EBI_DATA[7](2)
*
* GPY6[0] EBI_DATA[8](2)
* GPY6[1] EBI_DATA[9](2)
* GPY6[2] EBI_DATA[10](2)
* GPY6[3] EBI_DATA[11](2)
* GPY6[4] EBI_DATA[12](2)
* GPY6[5] EBI_DATA[13](2)
* GPY6[6] EBI_DATA[14](2)
* GPY6[7] EBI_DATA[15](2)
*/
for (i = 0; i < 8; i++) {
s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
}
}
