Exemplos de GPU_readData em C++ (Cpp)

Exemplo n.º 1

Arquivo: psxhw.c Projeto: CatalystG/PCSX-reARMed-PB

u32 psxHwRead32(u32 add) {
	u32 hard;

	switch (add) {
		case 0x1f801040:
			hard = sioRead8();
			hard |= sioRead8() << 8;
			hard |= sioRead8() << 16;
			hard |= sioRead8() << 24;
#ifdef PAD_LOG
			PAD_LOG("sio read32 ;ret = %x\n", hard);
#endif
			return hard;
#ifdef ENABLE_SIO1API
		case 0x1f801050:
			hard = SIO1_readData32();
			return hard;
#endif
#ifdef PSXHW_LOG
		case 0x1f801060:
			PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
			return psxHu32(0x1060);
#endif
#ifdef PSXHW_LOG
		case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
			return psxHu32(0x1070);
#endif
#ifdef PSXHW_LOG
		case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
			return psxHu32(0x1074);
#endif

		case 0x1f801810:
			hard = GPU_readData();
#ifdef PSXHW_LOG
			PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
#endif
			return hard;
		case 0x1f801814:
			gpuSyncPluginSR();
			hard = HW_GPU_STATUS;
			if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
				hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
#ifdef PSXHW_LOG
			PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
#endif
			return hard;

		case 0x1f801820: hard = mdecRead0(); break;
		case 0x1f801824: hard = mdecRead1(); break;

#ifdef PSXHW_LOG
		case 0x1f8010a0:
			PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
			return SWAPu32(HW_DMA2_MADR);
		case 0x1f8010a4:
			PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
			return SWAPu32(HW_DMA2_BCR);
		case 0x1f8010a8:
			PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
			return SWAPu32(HW_DMA2_CHCR);
#endif

#ifdef PSXHW_LOG
		case 0x1f8010b0:
			PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
			return SWAPu32(HW_DMA3_MADR);
		case 0x1f8010b4:
			PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
			return SWAPu32(HW_DMA3_BCR);
		case 0x1f8010b8:
			PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
			return SWAPu32(HW_DMA3_CHCR);
#endif

#ifdef PSXHW_LOG
/*		case 0x1f8010f0:
			PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
			return SWAPu32(HW_DMA_PCR); // dma rest channel
		case 0x1f8010f4:
			PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
			return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
#endif

		// time for rootcounters :)
		case 0x1f801100:
			hard = psxRcntRcount(0);
#ifdef PSXHW_LOG
			PSXHW_LOG("T0 count read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801104:
			hard = psxRcntRmode(0);
#ifdef PSXHW_LOG
			PSXHW_LOG("T0 mode read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801108:
			hard = psxRcntRtarget(0);
#ifdef PSXHW_LOG
			PSXHW_LOG("T0 target read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801110:
			hard = psxRcntRcount(1);
#ifdef PSXHW_LOG
			PSXHW_LOG("T1 count read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801114:
			hard = psxRcntRmode(1);
#ifdef PSXHW_LOG
			PSXHW_LOG("T1 mode read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801118:
			hard = psxRcntRtarget(1);
#ifdef PSXHW_LOG
			PSXHW_LOG("T1 target read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801120:
			hard = psxRcntRcount(2);
#ifdef PSXHW_LOG
			PSXHW_LOG("T2 count read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801124:
			hard = psxRcntRmode(2);
#ifdef PSXHW_LOG
			PSXHW_LOG("T2 mode read32: %x\n", hard);
#endif
			return hard;
		case 0x1f801128:
			hard = psxRcntRtarget(2);
#ifdef PSXHW_LOG
			PSXHW_LOG("T2 target read32: %x\n", hard);
#endif
			return hard;

		default:
			hard = psxHu32(add); 
#ifdef PSXHW_LOG
			PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
#endif
			return hard;
	}
#ifdef PSXHW_LOG
	PSXHW_LOG("*Known 32bit read at address %x\n", add);
#endif
	return hard;
}

Exemplo n.º 2

Arquivo: psxhw.c Projeto: kmooney/pcsxr

u32 psxHwRead32(u32 add) {
    u32 hard;

    switch (add) {
    case 0x1f801040:
        hard = sioRead8();
        hard |= sioRead8() << 8;
        hard |= sioRead8() << 16;
        hard |= sioRead8() << 24;
#ifdef PAD_LOG
        PAD_LOG("sio read32 ;ret = %x\n", hard);
#endif
        return hard;
#ifdef ENABLE_SIO1API
    case 0x1f801050:
        hard = SIO1_readData32();
#ifdef SIO1_LOG
        SIO1_LOG("sio1 read32 ;ret = %x\n", hard);
#endif
        return hard;
#endif
#ifdef PSXHW_LOG
    case 0x1f801060:
        PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
        return psxHu32(0x1060);
#endif
#ifdef PSXHW_LOG
    case 0x1f801070:
        PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070));
        return psxHu32(0x1070);
#endif
#ifdef PSXHW_LOG
    case 0x1f801074:
        PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074));
        return psxHu32(0x1074);
#endif

    case 0x1f801810:
        hard = GPU_readData();
#ifdef PSXHW_LOG
        PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
#endif
        return hard;
    case 0x1f801814:
        hard = gpuReadStatus();
#ifdef PSXHW_LOG
        PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
#endif
        return hard;

    case 0x1f801820:
        hard = mdecRead0();
        break;
    case 0x1f801824:
        hard = mdecRead1();
        break;

#ifdef PSXHW_LOG
    case 0x1f8010a0:
        PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
        return SWAPu32(HW_DMA2_MADR);
    case 0x1f8010a4:
        PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
        return SWAPu32(HW_DMA2_BCR);
    case 0x1f8010a8:
        PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
        return SWAPu32(HW_DMA2_CHCR);
#endif

#ifdef PSXHW_LOG
    case 0x1f8010b0:
        PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
        return SWAPu32(HW_DMA3_MADR);
    case 0x1f8010b4:
        PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
        return SWAPu32(HW_DMA3_BCR);
    case 0x1f8010b8:
        PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
        return SWAPu32(HW_DMA3_CHCR);
#endif

#ifdef PSXHW_LOG
    case 0x1f8010f0:
        PSXHW_LOG("DMA PCR 32bit read %x\n", HW_DMA_PCR);
        return SWAPu32(HW_DMA_PCR); // DMA control register
    case 0x1f8010f4:
        PSXHW_LOG("DMA ICR 32bit read %x\n", HW_DMA_ICR);
        return SWAPu32(HW_DMA_ICR); // DMA interrupt register (enable/ack)
#endif

    // time for rootcounters :)
    case 0x1f801100:
        hard = psxRcntRcount(0);
#ifdef PSXHW_LOG
        PSXHW_LOG("T0 count read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801104:
        hard = psxRcntRmode(0);
#ifdef PSXHW_LOG
        PSXHW_LOG("T0 mode read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801108:
        hard = psxRcntRtarget(0);
#ifdef PSXHW_LOG
        PSXHW_LOG("T0 target read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801110:
        hard = psxRcntRcount(1);
#ifdef PSXHW_LOG
        PSXHW_LOG("T1 count read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801114:
        hard = psxRcntRmode(1);
#ifdef PSXHW_LOG
        PSXHW_LOG("T1 mode read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801118:
        hard = psxRcntRtarget(1);
#ifdef PSXHW_LOG
        PSXHW_LOG("T1 target read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801120:
        hard = psxRcntRcount(2);
#ifdef PSXHW_LOG
        PSXHW_LOG("T2 count read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801124:
        hard = psxRcntRmode(2);
#ifdef PSXHW_LOG
        PSXHW_LOG("T2 mode read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801128:
        hard = psxRcntRtarget(2);
#ifdef PSXHW_LOG
        PSXHW_LOG("T2 target read32: %x\n", hard);
#endif
        return hard;
    case 0x1f801014:
        hard = psxHu32(add);
#ifdef PSXHW_LOG
        PSXHW_LOG("SPU delay [0x1014] read32: %8.8lx\n", hard);
#endif
        return hard;

    default:
        hard = psxHu32(add);
#ifdef PSXHW_LOG
        PSXHW_LOG("*Unknown 32bit read at address %x (0x%8.8lx)\n", add, hard);
#endif
        return hard;
    }
#ifdef PSXHW_LOG
    PSXHW_LOG("*Known 32bit read at address %x\n", add);
#endif
    return hard;
}