void i2s_unmask_handler(u32 dma_ch)
{
MSG("i2s_unmask_handler ch=%d\n",dma_ch);
if((dma_ch==GDMA_I2S_TX0)&&(pi2s_config->bTxDMAEnable))
{
GdmaI2sTx((u32)pi2s_config->pPage0TxBuf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_unmask_handler);
GdmaUnMaskChannel(GDMA_I2S_TX0);
}
if((dma_ch==GDMA_I2S_TX1)&&(pi2s_config->bTxDMAEnable))
{
GdmaI2sTx((u32)pi2s_config->pPage1TxBuf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_unmask_handler);
GdmaUnMaskChannel(GDMA_I2S_TX1);
}
#if defined(CONFIG_I2S_TXRX)
if((dma_ch==GDMA_I2S_RX0)&&(pi2s_config->bRxDMAEnable))
{
GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_unmask_handler);
GdmaUnMaskChannel(GDMA_I2S_RX0);
}
if((dma_ch==GDMA_I2S_RX1)&&(pi2s_config->bRxDMAEnable))
{
GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)pi2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_unmask_handler);
GdmaUnMaskChannel(GDMA_I2S_RX1);
}
#endif
}
void i2s_unmask_handler(u32 dma_ch)
{
MSG("i2s_unmask_handler ch=%d\n",dma_ch);
if(dma_ch==GDMA_I2S_TX1)
{
GdmaI2sTx(pi2s_config->page0buf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_handler, i2s_unmask_handler);
GdmaUnMaskChannel(GDMA_I2S_TX0);
}
else
{
GdmaI2sTx(pi2s_config->page1buf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_handler, i2s_unmask_handler);
GdmaUnMaskChannel(GDMA_I2S_TX1);
}
}
int chain_mode(void *unused) {
int i=0;
for(i=0;i< MAX_GDMA_CHANNEL; i++) {
GdmaMem2Mem(Src_phy[i], Dst_phy[i], PATTERN_LEN, Done);
}
GdmaUnMaskChannel(0); //kick of channel 0
#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
while(1) {
mdelay(1000);
}
#endif
return 1;
}
void Done(uint32_t Ch)
{
int i=0;
static int count[MAX_GDMA_CHANNEL];
if((++count[Ch] % SHOW_INTERVAL)==0) {
printk("Ch=%d is still alive\n", Ch);
}
for(i=0;i<PATTERN_LEN;i++) {
if(Dst[Ch][i]!=Src[Ch][i]) {
printk("***********<<WARNNING!!!>>*********\n");
printk("Ch=%d Check fail (Dst=%x Src=%x)\n",Ch, Dst[Ch][i], Src[Ch][i]);
printk("***********************************\n");
return;
}
}
DoneBit[Ch]=1;
//clear content of destination address
memset(Dst[Ch], 0, PATTERN_LEN);
#if defined (CHAIN)
//set up related fields for next transaction
GdmaMem2Mem(Src_phy[Ch], Dst_phy[Ch], PATTERN_LEN, Done);
/*If channel is MAX_GDMA_CHANNEL-1,
*it means channel 0 - channal (MAX_GDMA_CHANNEL-1) is ready
*just kill off channel 0 to start next chain-based transaction.
*/
if(Ch == (MAX_GDMA_CHANNEL-1)) {
GdmaUnMaskChannel(0);
}
#elif defined (CONCURRENT)
//set up related fields for next transaction
GdmaMem2Mem(Src_phy[Ch], Dst_phy[Ch], PATTERN_LEN, Done);
#endif
}
int i2s_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
#endif
{
int i ;
unsigned long flags, data;
i2s_config_type* ptri2s_config;
ptri2s_config = filp->private_data;
switch (cmd) {
case I2S_SRATE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
{
data = *(unsigned long*)(RALINK_SYSCTL_BASE+0x834);
data |=(1<<17);
*(unsigned long*)(RALINK_SYSCTL_BASE+0x834) = data;
data = *(unsigned long*)(RALINK_SYSCTL_BASE+0x834);
data &=~(1<<17);
*(unsigned long*)(RALINK_SYSCTL_BASE+0x834) = data;
audiohw_preinit();
}
if((arg>MAX_SRATE_HZ)||(arg<MIN_SRATE_HZ))
{
MSG("audio sampling rate %u should be %d ~ %d Hz\n", (u32)arg, MIN_SRATE_HZ, MAX_SRATE_HZ);
break;
}
ptri2s_config->srate = arg;
MSG("set audio sampling rate to %d Hz\n", ptri2s_config->srate);
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_TX_VOL:
spin_lock_irqsave(&ptri2s_config->lock, flags);
if((int)arg > 127)
{
ptri2s_config->txvol = 127;
}
else if((int)arg < 96)
{
ptri2s_config->txvol = 96;
}
else
ptri2s_config->txvol = arg;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_RX_VOL:
spin_lock_irqsave(&ptri2s_config->lock, flags);
if((int)arg > 63)
{
ptri2s_config->rxvol = 63;
}
else if((int)arg < 0)
{
ptri2s_config->rxvol = 0;
}
else
ptri2s_config->rxvol = arg;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_TX_ENABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_TXENABLE\n");
/* allocate tx buffer */
ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_txdma_addr);
if(ptri2s_config->pPage0TxBuf8ptr==NULL)
{
MSG("Allocate Tx Page Buffer Failed\n");
return -1;
}
ptri2s_config->pPage1TxBuf8ptr = ptri2s_config->pPage0TxBuf8ptr + I2S_PAGE_SIZE;
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
#if defined(CONFIG_I2S_MMAP)
ptri2s_config->pMMAPTxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i];
#else
if(ptri2s_config->pMMAPTxBufPtr[i]==NULL)
ptri2s_config->pMMAPTxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
#endif
}
#if defined(I2S_FIFO_MODE)
#else
GdmaI2sTx((u32)ptri2s_config->pPage0TxBuf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_unmask_handler);
GdmaI2sTx((u32)ptri2s_config->pPage1TxBuf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_unmask_handler);
#endif
i2s_reset_tx_config(ptri2s_config);
ptri2s_config->bTxDMAEnable = 1;
i2s_tx_config(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
i2s_clock_enable(ptri2s_config);
audiohw_set_lineout_vol(1, ptri2s_config->txvol, ptri2s_config->txvol);
i2s_tx_enable(ptri2s_config);
#if defined(I2S_FIFO_MODE)
#else
GdmaUnMaskChannel(GDMA_I2S_TX0);
#endif
data = i2s_inw(RALINK_REG_INTENA);
data |=0x0400;
i2s_outw(RALINK_REG_INTENA, data);
MSG("I2S_TXENABLE done\n");
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_TX_DISABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_TXDISABLE\n");
i2s_tx_disable(ptri2s_config);
i2s_reset_tx_config(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
i2s_clock_disable(ptri2s_config);
//i2s_tx_disable(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
{
data = i2s_inw(RALINK_REG_INTENA);
data &= 0xFFFFFBFF;
i2s_outw(RALINK_REG_INTENA, data);
}
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
if(ptri2s_config->pMMAPTxBufPtr[i] != NULL)
{
#if defined(CONFIG_I2S_MMAP)
dma_unmap_single(NULL, i2s_mmap_addr[i], I2S_PAGE_SIZE, DMA_TO_DEVICE);
#endif
kfree(ptri2s_config->pMMAPTxBufPtr[i]);
ptri2s_config->pMMAPTxBufPtr[i] = NULL;
}
}
pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr);
ptri2s_config->pPage0TxBuf8ptr = NULL;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_RX_ENABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_RXENABLE\n");
/* allocate rx buffer */
ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_rxdma_addr);
if(ptri2s_config->pPage0RxBuf8ptr==NULL)
{
MSG("Allocate Rx Page Buffer Failed\n");
return -1;
}
ptri2s_config->pPage1RxBuf8ptr = ptri2s_config->pPage0RxBuf8ptr + I2S_PAGE_SIZE;
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
if(ptri2s_config->pMMAPRxBufPtr[i]==NULL)
ptri2s_config->pMMAPRxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
}
#if defined(I2S_FIFO_MODE)
#else
GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_unmask_handler);
GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_unmask_handler);
#endif
i2s_reset_rx_config(ptri2s_config);
ptri2s_config->bRxDMAEnable = 1;
i2s_rx_config(ptri2s_config);
#if defined(I2S_FIFO_MODE)
#else
GdmaUnMaskChannel(GDMA_I2S_RX0);
#endif
if(ptri2s_config->bTxDMAEnable==0)
i2s_clock_enable(ptri2s_config);
#if defined(CONFIG_I2S_TXRX)
audiohw_set_linein_vol(ptri2s_config->rxvol, ptri2s_config->rxvol);
#endif
i2s_rx_enable(ptri2s_config);
data = i2s_inw(RALINK_REG_INTENA);
data |=0x0400;
i2s_outw(RALINK_REG_INTENA, data);
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_RX_DISABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_RXDISABLE\n");
i2s_reset_rx_config(ptri2s_config);
if(ptri2s_config->bTxDMAEnable==0)
i2s_clock_disable(ptri2s_config);
i2s_rx_disable(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
{
data = i2s_inw(RALINK_REG_INTENA);
data &= 0xFFFFFBFF;
i2s_outw(RALINK_REG_INTENA, data);
}
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
if(ptri2s_config->pMMAPRxBufPtr[i] != NULL)
kfree(ptri2s_config->pMMAPRxBufPtr[i]);
ptri2s_config->pMMAPRxBufPtr[i] = NULL;
}
pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr);
ptri2s_config->pPage0RxBuf8ptr = NULL;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_PUT_AUDIO:
//MSG("I2S_PUT_AUDIO\n");
#if defined(I2S_FIFO_MODE)
{
long* pData ;
//MSG("I2S_PUT_AUDIO FIFO\n");
copy_from_user(ptri2s_config->pMMAPTxBufPtr[0], (char*)arg, I2S_PAGE_SIZE);
pData = ptri2s_config->pMMAPTxBufPtr[0];
for(i = 0 ; i < I2S_PAGE_SIZE>>2 ; i++ )
{
int j;
unsigned long status = i2s_inw(I2S_FF_STATUS);
while((status&0x0F)==0)
{
for(j = 0 ; j < 50 ; j++);
status = i2s_inw(I2S_FF_STATUS);
}
*((volatile uint32_t *)(I2S_TX_FIFO_WREG)) = cpu_to_le32(*pData);
if(i==16)
MSG("I2S_PUT_AUDIO FIFO[0x%08X]\n", *pData);
pData++;
}
}
break;
#else
do{
spin_lock_irqsave(&ptri2s_config->lock, flags);
if(((ptri2s_config->tx_w_idx+4)%MAX_I2S_PAGE)!=ptri2s_config->tx_r_idx)
{
ptri2s_config->tx_w_idx = (ptri2s_config->tx_w_idx+1)%MAX_I2S_PAGE;
//printk("put TB[%d] for user write\n",ptri2s_config->tx_w_idx);
#if defined(CONFIG_I2S_MMAP)
put_user(ptri2s_config->tx_w_idx, (int*)arg);
#else
copy_from_user(ptri2s_config->pMMAPTxBufPtr[ptri2s_config->tx_w_idx], (char*)arg, I2S_PAGE_SIZE);
#endif
pi2s_status->txbuffer_len++;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
}
else
{
/* Buffer Full */
//printk("TBF tr=%d, tw=%d\n", ptri2s_config->tx_r_idx, ptri2s_config->tx_w_idx);
pi2s_status->txbuffer_ovrun++;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
}
}while(1);
break;
#endif
case I2S_GET_AUDIO:
#if defined(I2S_FIFO_MODE)
{
long* pData ;
pData = ptri2s_config->pMMAPRxBufPtr[0];
for(i = 0 ; i < I2S_PAGE_SIZE>>2 ; i++ )
{
int j;
unsigned long status = i2s_inw(I2S_FF_STATUS);
while((status&0x0F0)==0)
{
for(j = 0 ; j < 50 ; j++);
status = i2s_inw(I2S_FF_STATUS);
}
*pData = i2s_inw(I2S_RX_FIFO_RREG);
if(i==16)
MSG("I2S_GET_AUDIO FIFO[0x%08X]\n", *pData);
pData++;
}
copy_to_user((char*)arg, ptri2s_config->pMMAPRxBufPtr[0], I2S_PAGE_SIZE);
}
break;
#else
do{
spin_lock_irqsave(&ptri2s_config->lock, flags);
if(ptri2s_config->rx_r_idx!=ptri2s_config->rx_w_idx)
{
copy_to_user((char*)arg, ptri2s_config->pMMAPRxBufPtr[ptri2s_config->rx_r_idx], I2S_PAGE_SIZE);
ptri2s_config->rx_r_idx = (ptri2s_config->rx_r_idx+1)%MAX_I2S_PAGE;
pi2s_status->rxbuffer_len--;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
}
else
{
/* Buffer Full */
//printk("RBF rr=%d, rw=%d\n", ptri2s_config->rx_r_idx, ptri2s_config->rx_w_idx);
pi2s_status->rxbuffer_ovrun++;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
}
}while(1);
break;
#endif
case I2S_DEBUG_CLKGEN:
case I2S_DEBUG_INLBK:
case I2S_DEBUG_EXLBK:
case I2S_DEBUG_CODECBYPASS:
case I2S_DEBUG_FMT:
case I2S_DEBUG_RESET:
i2s_debug_cmd(cmd, arg);
break;
default :
MSG("i2s_ioctl: command format error\n");
}
return 0;
}
int i2s_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
{
int x;
unsigned long flags, data;
i2s_config_type* ptri2s_config;
ptri2s_config = filp->private_data;
switch (cmd) {
case I2S_SRATE:
if((arg>MAX_SRATE_HZ)||(arg<MIN_SRATE_HZ))
{
MSG("audio sampling rate %d should be %d ~ %d Hz\n", arg, MIN_SRATE_HZ, MAX_SRATE_HZ);
break;
}
ptri2s_config->srate = arg;
MSG("set audio sampling rate to %d Hz\n", ptri2s_config->srate);
break;
case I2S_VOL:
if(((int)arg>MAX_VOL_DB)||((int)arg<MIN_VOL_DB))
{
MSG("audio volumn %d should be %d ~ %d dB\n", arg, MIN_VOL_DB, MAX_VOL_DB);
break;
}
ptri2s_config->vol = arg;
x = 2*arg+255;
audiohw_set_master_vol(x, x);
MSG("set audio volumn to %d dB\n", ptri2s_config->vol);
break;
case I2S_ENABLE:
ptri2s_config->isr_cnt = 0;
pi2s_status->buffer_unrun = 0;
pi2s_status->buffer_ovrun = 0;
pi2s_status->txdmafault = 0;
pi2s_status->ovrun = 0;
pi2s_status->unrun = 0;
pi2s_status->thres = 0;
pi2s_status->buffer_len = 0;
data = i2s_inw(RALINK_REG_INTENA);
//data |=0x0400;
data &=0xFFBFF;
i2s_outw(RALINK_REG_INTENA, data);
MSG("i2s audio enable\n");
if(i2s_dev_open(ptri2s_config)!=I2S_OK)
{
i2s_release(inode, filp);
return -1;
}
wake_up_interruptible(&(ptri2s_config->i2s_qh));
break;
case I2S_DISABLE:
MSG("i2s audio disable\n");
data = i2s_inw(RALINK_REG_INTENA);
data &= 0xFFFFFBFF;
i2s_outw(RALINK_REG_INTENA, data);
ptri2s_config->bDMAStart = 0;
i2s_dev_close(ptri2s_config);
wake_up_interruptible(&(ptri2s_config->i2s_qh));
break;
case I2S_GET_WBUF:
#ifdef I2S_FIFO_MODE
{
int i,j;
long* pBufPtr = pi2s_config->pMMAPBufPtr+(pi2s_config->w_idx)*I2S_PAGE_SIZE;
for(i=0; i<I2S_PAGE_SIZE>>2; i++)
{
long status;
i2s_outw(I2S_FIFO_WREG, bswap_32(pBufPtr[i]));
while(1)
{
status = i2s_inw(I2S_FF_STATUS);
if(status&0x00F!=0)
break;
}
}
ptri2s_config->w_idx = (ptri2s_config->w_idx+1)%MAX_I2S_PAGE;
(int)(*(int*)arg) = (int)ptri2s_config->w_idx;
break;
}
#endif
if(ptri2s_config->bDMAStart==0)
{
GdmaI2sTx(ptri2s_config->page0buf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_handler, i2s_unmask_handler);
GdmaI2sTx(ptri2s_config->page1buf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_handler, i2s_unmask_handler);
ptri2s_config->bDMAStart=1;
GdmaUnMaskChannel(GDMA_I2S_TX0);
}
do{
spin_lock_irqsave(&ptri2s_config->lock, flags);
if(((ptri2s_config->w_idx+1)%MAX_I2S_PAGE)!=ptri2s_config->r_idx)
{
ptri2s_config->w_idx = (ptri2s_config->w_idx+1)%MAX_I2S_PAGE;
(int)(*(int*)arg) = (int)ptri2s_config->w_idx;
pi2s_status->buffer_len++;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
}
else
{
/* Buffer Full */
//printk("BF w=%d, r=%d\n", ptri2s_config->w_idx, ptri2s_config->r_idx);
pi2s_status->buffer_ovrun++;
ptri2s_config->bSleep = 1;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
interruptible_sleep_on(&(ptri2s_config->i2s_qh));
}
}while(1);
break;
default :
MSG("i2s_ioctl: command format error\n");
}
return 0;
}
