/** Disables CPU interrupts and returns the interrupt state prior to the disable operation. @retval TRUE CPU interrupts were enabled on entry to this call. @retval FALSE CPU interrupts were disabled on entry to this call. **/ BOOLEAN EFIAPI SaveAndDisableInterrupts ( VOID ) { BOOLEAN InterruptState; InterruptState = GetInterruptState (); DisableInterrupts (); return InterruptState; }
/** Places the CPU in a sleep state until an interrupt is received. Places the CPU in a sleep state until an interrupt is received. If interrupts are disabled prior to calling this function, then the CPU will be placed in a sleep state indefinitely. **/ VOID EFIAPI CpuSleep ( VOID ) { UINT64 Tpr; // // It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting. // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts. // If interrupts are enabled, then just use current TRP setting. // if (GetInterruptState ()) { // // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting. // PalCall (PAL_HALT_LIGHT, 0, 0, 0); } else { // // If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT. // // // Save TPR // Tpr = AsmReadTpr(); // // Set TPR.mmi to mask all external interrupts // AsmWriteTpr (BIT16 | Tpr); PalCall (PAL_HALT_LIGHT, 0, 0, 0); // // Restore TPR // AsmWriteTpr (Tpr); } }