AGESA_STATUS
GfxConfigPostInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
GFX_PLATFORM_CONFIG *Gfx;
AMD_POST_PARAMS *PostParamsPtr;
AGESA_STATUS Status;
PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n");
Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
ASSERT (Gfx != NULL);
if (Gfx != NULL) {
LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
if (GnbBuildOptions.IgfxModeAsPcieEp) {
Gfx->GfxControllerMode = GfxControllerPcieEndpointMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
} else {
Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
}
Gfx->StdHeader = StdHeader;
Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl;
Gfx->ForceGfxMode = GfxEnableAuto;
Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType;
Gfx->GmcClockGating = OptionEnabled;
Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGateStutterOnly ? GmcPowerGatingStutterOnly : GmcPowerGatingWidthStutter;
Gfx->UmaSteering = Garlic;
GNB_DEBUG_CODE (
GfxConfigDebugDump (Gfx);
);
VOID *
GnbAllocateHeapBufferAndClear (
IN UINT32 Handle,
IN UINTN Length,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
VOID *Buffer;
Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader);
if (Buffer != NULL) {
LibAmdMemFill (Buffer, 0x00, Length, StdHeader);
}
return Buffer;
}
AGESA_STATUS
PcieAlibBuildAcpiTableV2 (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT VOID **AlibSsdtPtr
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
VOID *AlibSsdtBuffer;
VOID *AlibSsdtTable;
UINTN AlibSsdtlength;
UINT32 AmlObjName;
VOID *AmlObjPtr;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTableV2 Enter\n");
AgesaStatus = AGESA_SUCCESS;
AlibSsdtTable = GnbFmAlibGetBaseTable (StdHeader);
AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtTable)->TableLength;
if (*AlibSsdtPtr == NULL) {
AlibSsdtBuffer = GnbAllocateHeapBuffer (
AMD_ACPI_ALIB_BUFFER_HANDLE,
AlibSsdtlength,
StdHeader
);
ASSERT (AlibSsdtBuffer != NULL);
if (AlibSsdtBuffer == NULL) {
return AGESA_ERROR;
}
*AlibSsdtPtr = AlibSsdtBuffer;
} else {
AlibSsdtBuffer = *AlibSsdtPtr;
}
// Check length of port data
ASSERT (sizeof (_ALIB_PORT_DATA) <= 20);
// Check length of global data
ASSERT (sizeof (_ALIB_GLOBAL_DATA) <= 32);
// Copy template to buffer
LibAmdMemCopy (AlibSsdtBuffer, AlibSsdtTable, AlibSsdtlength, StdHeader);
// Update table OEM fields.
LibAmdMemCopy (
(VOID *) &((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->OemId,
(VOID *) &GnbBuildOptions.OemIdString,
sizeof (GnbBuildOptions.OemIdString),
StdHeader);
LibAmdMemCopy (
(VOID *) &((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->OemTableId,
(VOID *) &GnbBuildOptions.OemTableIdString,
sizeof (GnbBuildOptions.OemTableIdString),
StdHeader);
//
// Update register base base
//
PcieAlibUpdateGnbData (AlibSsdtBuffer, StdHeader);
//
// Update transfer block
//
AmlObjName = STRING_TO_UINT32 ('A', 'D', 'A', 'T');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
if (AmlObjPtr != NULL) {
AmlObjPtr = (UINT8 *) AmlObjPtr + 10;
}
// Dispatch function from table
Status = GnbLibDispatchFeaturesV2 (&AlibDispatchTableV2[0], AmlObjPtr, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (AgesaStatus != AGESA_SUCCESS) {
//Shrink table length to size of the header
((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
}
ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTableV2 Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
PcieAlibBuildAcpiTable (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT VOID **AlibSsdtPtr
)
{
AGESA_STATUS Status;
UINT32 AmlObjName;
PCIe_PLATFORM_CONFIG *Pcie;
PP_FUSE_ARRAY *PpFuseArray;
VOID *AlibSsdtBuffer;
VOID *AmlObjPtr;
UINT8 SclkVidArray[4];
UINT8 BootUpVid;
UINT8 BootUpVidIndex;
UINT8 Gen1VidIndex;
UINTN Index;
UINTN AlibSsdtlength;
Status = AGESA_SUCCESS;
AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength;
if (*AlibSsdtPtr == NULL) {
AlibSsdtBuffer = GnbAllocateHeapBuffer (
AMD_ACPI_ALIB_BUFFER_HANDLE,
AlibSsdtlength,
StdHeader
);
ASSERT (AlibSsdtBuffer != NULL);
if (AlibSsdtBuffer == NULL) {
return AGESA_ERROR;
}
*AlibSsdtPtr = AlibSsdtBuffer;
} else {
AlibSsdtBuffer = *AlibSsdtPtr;
}
// Copy template to buffer
LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
// Set PCI MMIO configuration
// AmlObjName = '10DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '1');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
if (AmlObjPtr != NULL) {
UINT64 MsrReg;
LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
if ((MsrReg & BIT0) != 0 && (MsrReg & 0xFFFFFFFF00000000) == 0) {
*(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrReg & 0xFFFFF00000);
} else {
Status = AGESA_ERROR;
}
} else {
Status = AGESA_ERROR;
}
// Set voltage configuration
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
// AmlObjName = '30DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '3');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid;
} else {
Status = AGESA_ERROR;
}
} else {
Status = AGESA_ERROR;
}
GnbLibPciRead (
MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
AccessWidth32,
&SclkVidArray[0],
StdHeader
);
Gen1VidIndex = 0;
BootUpVidIndex = 0;
BootUpVid = 0xff;
for (Index = 0; Index < 4; Index++) {
if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) {
Gen1VidIndex = (UINT8) Index;
}
if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < BootUpVid) {
BootUpVid = SclkVidArray[Index];
BootUpVidIndex = (UINT8) Index;
}
}
// AmlObjName = '40DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '4');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = Gen1VidIndex;
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '50DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '5');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = BootUpVidIndex;
} else {
Status = AGESA_ERROR;
}
// Set PCIe configuration
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
// AmlObjName = '20DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '2');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = Pcie->PsppPolicy;
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '60DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '6');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortMaxSpeedCallback,
(UINT8*)((UINT8*)AmlObjPtr + 7),
Pcie
);
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '80DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '8');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortOverrideSpeedCallback,
(UINT8*)((UINT8*)AmlObjPtr + 7),
Pcie
);
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '70DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '7');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortInfoCallback,
(UINT8*)((UINT8*)AmlObjPtr + 4),
Pcie
);
} else {
Status = AGESA_ERROR;
}
} else {
ASSERT (FALSE);
Status = AGESA_ERROR;
}
if (Status == AGESA_SUCCESS) {
Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader);
}
if (Status != AGESA_SUCCESS) {
//Shrink table length to size of the header
((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
}
ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
return Status;
}
AGESA_STATUS
GfxSamuInit (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
UINT32 D0F0xBC_xC00C0000;
GNB_HANDLE *GnbHandle;
VOID *ControlXBuffer;
VOID *AlignedControlXBuffer;
VOID *PatchYBuffer;
VOID *AlignedPatchYBuffer;
SAMU_BOOT_CONTROL *SamuBootControl;
UINT32 D0F0xBC_x800000A4;
UINT32 GMMx22000;
UINT32 GMMx22004;
UINT32 GMMx22008;
UINT32 GMMx2200C;
UINT32 LoopCount;
BOOLEAN SamuUseF1dPatch;
BOOLEAN SamuPatchEnabled;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbSamuInit Enter\n");
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
ASSERT (GnbHandle != NULL);
GnbRegisterReadKB (GnbHandle, 0x4, 0xc00c0000,
&D0F0xBC_xC00C0000, 0, GnbLibGetHeader (Gfx));
SamuPatchEnabled = GnbBuildOptions.CfgSamuPatchEnabled;
IDS_OPTION_HOOK (IDS_GNB_LOAD_SAMU_PATCH, &SamuPatchEnabled, GnbLibGetHeader (Gfx));
if ((((D0F0xBC_xC00C0000) & BIT24) == 0) &&
(SamuPatchEnabled == TRUE)) {
// Decide which version of the patch to use
SamuUseF1dPatch = TRUE;
GMMx22008 = 0x29;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008,
&GMMx22008, 0, GnbLibGetHeader (Gfx));
GnbRegisterReadKB (GnbHandle, 0x12, 0x2200C,
&GMMx2200C, 0, GnbLibGetHeader (Gfx));
IDS_HDT_CONSOLE (GNB_TRACE, " SAMSAB:29=%08x\n", GMMx2200C);
if (GMMx2200C == 0x80000001) {
SamuUseF1dPatch = FALSE;
}
ControlXBuffer = GnbAllocateHeapBufferAndClear (AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
ASSERT (ControlXBuffer != NULL);
if (ControlXBuffer == NULL) {
return AGESA_ERROR;
}
AlignedControlXBuffer = (VOID *) (((UINTN)ControlXBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE));
PatchYBuffer = GnbAllocateHeapBuffer (AMD_GNB_SAMU_PATCH_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
ASSERT (PatchYBuffer != NULL);
if (PatchYBuffer == NULL) {
return AGESA_ERROR;
}
AlignedPatchYBuffer = (VOID *) (((UINTN)PatchYBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE));
// Copy samu firmware patch to PatchYBuffer
if (SamuUseF1dPatch == TRUE) {
LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKB[0],
SamuPatchKBHeader[1], GnbLibGetHeader (Gfx));
} else {
LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKBUnf1[0],
SamuPatchKBHeaderUnf1[1], GnbLibGetHeader (Gfx));
}
// WBINVD
LibAmdWriteBackInvalidateCache ();
// Load boot control structure
SamuBootControl = (SAMU_BOOT_CONTROL *)AlignedControlXBuffer;
SamuBootControl->BootControl = 0x3;
SamuBootControl->KernelAddrLo = (UINTN)AlignedPatchYBuffer;
SamuBootControl->KernelAddrHi = ((((UINT64)(UINTN)AlignedPatchYBuffer) >> 32) & 0xFF);
if (SamuUseF1dPatch == TRUE) {
SamuBootControl->TweakSelect = 0xBB027E1F;
SamuBootControl->KeySelect = 0x8E174F83;
} else {
SamuBootControl->TweakSelect = 0x0;
SamuBootControl->KeySelect = 0x0;
}
// Write 0x0 to SAM_CGC_HOST_CTRL to release the clock-gating of SAMU
GMMx22000 = 0x3;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GMMx22004 = 0x0;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
// Write (physical address of boot control structure)>>8 into SAM_SAB_INIT_TLB_CONFIG (Location X >> 8)
GMMx22008 = 0x4;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, &GMMx22008, 0, GnbLibGetHeader (Gfx));
GMMx2200C = ((UINTN) AlignedControlXBuffer) >> 8;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x2200C, &GMMx2200C, 0, GnbLibGetHeader (Gfx));
// Write 0x0 to SAM_RST_HOST_SOFT_RESET
GMMx22000 = 0x1;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GMMx22004 = 0x0;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
// Write 0x2 to SAM_SCRATCH_0 to start the firmware boot
GMMx22000 = 0x38;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GMMx22004 = 0x2;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
// Poll SAM_RST_HOST_SOFT_RST_RDY and wait for HOST_RDY
do {
// Write 0x2 to SAM_SCRATCH_0 to start the firmware boot
GMMx22000 = 0x51;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GnbRegisterReadKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
} while ((GMMx22004 & BIT0) == 0);
// Clear the allocated memory ranges, locations X and Y (write 0), issue WBINVD
LibAmdMemFill (ControlXBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
LibAmdMemFill (PatchYBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
LibAmdWriteBackInvalidateCache ();
// Confirm read of SMC_DRAM_ACCESS_CNTL is 0x1
D0F0xBC_x800000A4 = 0;
for (LoopCount = 0; LoopCount < 0x00FFFFFF; LoopCount++) {
GnbRegisterReadKB (GnbHandle, 0x4, 0x800000A4, &D0F0xBC_x800000A4, 0, GnbLibGetHeader (Gfx));
if ((D0F0xBC_x800000A4 & BIT0) != 0) {
break;
}
}
ASSERT ((D0F0xBC_x800000A4 & BIT0) != 0);
}
AGESA_STATUS
GnbLoadBuildOptionDataML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GNB_HANDLE *GnbHandle;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
UINT32 D0F0xBC_xC01040D0;
CPU_LOGICAL_ID LogicalCpuid;
D18F3xA0_STRUCT D18F3xA0;
Status = AGESA_SUCCESS;
GnbBuildOptionData = (GNB_BUILD_OPTIONS_ML *) GnbAllocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, sizeof (GNB_BUILD_OPTIONS_ML), StdHeader);
ASSERT (GnbBuildOptionData != NULL);
GnbHandle = GnbGetHandle (StdHeader);
GnbBuildOptionData->GnbCommonOptions.CfgScsSupport = GnbBuildOptionsML.GnbCommonOptions.CfgScsSupport;
GnbBuildOptionData->GnbCommonOptions.CfgUmaSteering = GnbBuildOptionsML.GnbCommonOptions.CfgUmaSteering;
GnbBuildOptionData->GnbCommonOptions.GmcPowerGating = GnbBuildOptionsML.GnbCommonOptions.GmcPowerGating;
GnbBuildOptionData->GnbCommonOptions.CfgGmcClockGating = GnbBuildOptionsML.GnbCommonOptions.CfgGmcClockGating;
GnbBuildOptionData->GnbCommonOptions.CfgOrbDynWakeEnable = GnbBuildOptionsML.GnbCommonOptions.CfgOrbDynWakeEnable;
GnbBuildOptionData->GnbCommonOptions.CfgOrbClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgOrbClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.CfgIommuL1ClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgIommuL1ClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.CfgIommuL2ClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgIommuL2ClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.LclkDeepSleepEn = GnbBuildOptionsML.GnbCommonOptions.LclkDeepSleepEn;
GnbBuildOptionData->GnbCommonOptions.LclkDpmEn = GnbBuildOptionsML.GnbCommonOptions.LclkDpmEn;
GnbBuildOptionData->GnbCommonOptions.CfgIocLclkClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgIocLclkClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.CfgBapmSupport = GnbBuildOptionsML.GnbCommonOptions.CfgBapmSupport;
GnbBuildOptionData->GnbCommonOptions.CfgDcTdpEnable = GnbBuildOptionsML.GnbCommonOptions.CfgDcTdpEnable;
GnbBuildOptionData->CfgLhtcSupport = GnbBuildOptionsML.CfgLhtcSupport;
GnbBuildOptionData->CfgSviRevision = GnbBuildOptionsML.CfgSviRevision;
GnbBuildOptionData->CfgSamuPatchEnabled = GnbBuildOptionsML.CfgSamuPatchEnabled;
GnbBuildOptionData->CfgTdcSupport = GnbBuildOptionsML.CfgTdcSupport;
GnbBuildOptionData->CfgNativeGen1PLL = GnbBuildOptionsML.CfgNativeGen1PLL;
GnbBuildOptionData->CfgPciePhyIsolationEnable = GnbBuildOptionsML.CfgPciePhyIsolationEnable;
GnbBuildOptionData->CfgLinkBwNotificationEn = GnbBuildOptionsML.CfgLinkBwNotificationEn;
GnbBuildOptionData->CfgBatteryBoostEn = UserOptions.CfgBatteryBoostEn;
GnbBuildOptionData->CfgSpgClockGatingEnable = GnbBuildOptionsML.CfgSpgClockGatingEnable;
GnbBuildOptionData->CfgPspDpmEn = GnbBuildOptionsML.CfgPspDpmEn;
GnbBuildOptionData->CfgSMUServiceEnablementBitMap = GnbBuildOptionsML.CfgSMUServiceEnablementBitMap;
GnbBuildOptionData->CfgUseSMUServices = GnbBuildOptionsML.CfgUseSMUServices;
// Check for BAPM capability
GnbRegisterReadML (GnbHandle, D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0, 0, StdHeader);
GetLogicalIdOfCurrentCore (&LogicalCpuid, StdHeader);
if (((LogicalCpuid.Family & AMD_FAMILY_16_ML) != 0)
&& ((LogicalCpuid.Revision & AMD_F16_ML_A0) != 0)
&& (D18F3xA0.Field.ConfigId < 35)) {
// BAPM is not supported on A0 ES1 config IDs
// Reduce SMU service enablement to supported services
GnbBuildOptionData->CfgSMUServiceEnablementBitMap = 0x003C0040ul;
}
IDS_HDT_CONSOLE (GNB_TRACE, "SMUServiceEnablementBitMap = 0x%x\n", GnbBuildOptionData->CfgSMUServiceEnablementBitMap);
IDS_OPTION_HOOK (IDS_GNB_LOAD_BUILD_OPTIONS, GnbBuildOptionData, StdHeader);
// Check fuse state of BBB feature.
GnbRegisterReadML (GnbHandle, D0F0xBC_xC01040D0_TYPE, D0F0xBC_xC01040D0_ADDRESS, &D0F0xBC_xC01040D0, 0, StdHeader);
if ((D0F0xBC_xC01040D0 & BIT15) == 0) {
GnbBuildOptionData->CfgBatteryBoostEn = FALSE;
}
GnbDumpBuildOptionDataML (GnbBuildOptionData);
return Status;
}
