AGESA_STATUS
PcieSbAgetAlinkIoAddress (
OUT UINT16 *AlinkPort,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 AlinkPortIndex;
AlinkPortIndex = 0xE0;
GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader);
GnbLibIoRead (0xCD7, AccessWidth8, AlinkPort, StdHeader);
AlinkPortIndex = 0xE1;
GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader);
GnbLibIoRead (0xCD7, AccessWidth8, (VOID*) ((UINT8*) AlinkPort + 1), StdHeader);
if (&AlinkPort == 0) {
return AGESA_UNSUPPORTED;
}
return AGESA_SUCCESS;
}
VOID
GfxFillSbMmioBaseAddress (
IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
IN GFX_PLATFORM_CONFIG *Gfx
)
{
UINT8 Index;
UINT32 SbMmioBaseAddress;
SbMmioBaseAddress = 0;
//Read Dword from PMIO 24h. SB PMIO region supports only byte read.
for (Index = 0x24; Index < 0x28; Index++) {
GnbLibIoWrite (SB_IOMAP_REGCD6, AccessWidth8, &Index, GnbLibGetHeader (Gfx));
GnbLibIoRead (SB_IOMAP_REGCD7, AccessWidth8, &(((UINT8*) &SbMmioBaseAddress)[Index - 0x24]), GnbLibGetHeader (Gfx));
}
// If MMIO is enabled and set for memory(not IO) then set MMIO_Base_Addr parameter.
if ((SbMmioBaseAddress & (SB_MMIO_IO_MAPPED_ENABLE | SB_MMIO_DECODE_ENABLE)) == SB_MMIO_DECODE_ENABLE) {
IntegratedInfoTable->ulSB_MMIO_Base_Addr = (ULONG) (SbMmioBaseAddress & (~SB_MMIO_DECODE_ENABLE)) ;
} else {
IntegratedInfoTable->ulSB_MMIO_Base_Addr = 0;
}
IDS_HDT_CONSOLE (GFX_MISC, " ulSB_MMIO_Base_Addr = 0x%x\n", IntegratedInfoTable->ulSB_MMIO_Base_Addr);
}
