AGESA_STATUS
GnbEarlierInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT32 D0F0xBC_xC00C002C;
FIRMWARE_HEADER_V7 *SmuFwHeader;
UINTN SmuFwSize;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
UINT32 PspMBox;
AgesaStatus = AGESA_SUCCESS;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEarlierInitTableBeforeSmuML,
0,
0,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
SmuFwHeader = NULL;
GnbRegisterReadML (GnbHandle, D0F0xBC_xC00C002C_TYPE, D0F0xBC_xC00C002C_ADDRESS, &D0F0xBC_xC00C002C, 0, StdHeader);
D0F0xBC_xC00C002C &= (BIT1 + BIT2 + BIT3 + BIT4 + BIT5);
IDS_HDT_CONSOLE (GNB_TRACE, " D0F0xBC_xC00C002C = 0x%x\n", D0F0xBC_xC00C002C);
Status = GnbLoadBuildOptionDataML (StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
//Load the SMU for non secure part & blank part
if ((D0F0xBC_xC00C002C == 0) || (D0F0xBC_xC00C002C == BIT5 + BIT3)) {
Status = GnbGetSmuFirmwareML ((UINTN *)&SmuFwHeader, &SmuFwSize);
ASSERT (SmuFwHeader != NULL);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GnbSmuFirmwareLoadV7 (GnbHandle, SmuFwHeader, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
} else {
Status = GnbPspMBoxRead (&PspMBox, GnbHandle, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, " PSP Mailbox Status = 0x%x\n", PspMBox);
if (Status == AGESA_SUCCESS) {
if ((PspMBox & MBOX_STATUS_RECOVERY) == MBOX_STATUS_RECOVERY) {
/// SET CfgUseSMUServices flag for recovery mode
GnbBuildOptionData->CfgUseSMUServices = FALSE;
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Exit [0x%x]\n", Status);
return AgesaStatus;
}
AGESA_STATUS
GnbEarlyInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT32 Property;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
Property = TABLE_PROPERTY_DEFAULT;
Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? TABLE_PROPERTY_NMI_SYNCFLOOD : 0;
IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG, GnbHandle, StdHeader);
GnbInitSmuBiosTableML (StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEarlyInitTableML,
Property,
0,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (GnbBuildOptionData->CfgUseSMUServices == TRUE) {
GnbRequestVddNbPminML (GnbHandle, StdHeader);
}
Status = GfxGBifEnableML (StdHeader);
ASSERT (Status == AGESA_SUCCESS);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GnbMidInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
UINT32 Property;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT8 SclkDid;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
ASSERT (GnbHandle != NULL);
Property = TABLE_PROPERTY_DEAFULT;
Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED;
Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0;
Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? TABLE_PROPERTY_ORB_CLK_GATING : 0;
Property |= GnbBuildOptions.CfgIocLclkClockGatingEnable ? TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING : 0;
Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING : 0;
Property |= GnbFmCheckIommuPresent (GnbHandle, StdHeader) ? 0: TABLE_PROPERTY_IOMMU_DISABLED;
Property |= GnbBuildOptions.SmuSclkClockGatingEnable ? TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING : 0;
IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) == 0) {
Status = GnbEnableIommuMmioV4 (GnbHandle, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GnbIommuMidInit (StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
//
// Set sclk to 100Mhz
//
SclkDid = GfxRequestSclkTNS3Save (
GfxLibCalculateDidTN (98 * 100, StdHeader),
StdHeader
);
Status = GnbProcessTable (
GnbHandle,
GnbMidInitTableTN,
Property,
GNB_TABLE_FLAGS_FORCE_S3_SAVE,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
//
// Restore Sclk
//
GfxRequestSclkTNS3Save (
SclkDid,
StdHeader
);
GnbCgttOverrideTN (Property, StdHeader);
Status = GnbLclkDpmInitTN (StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GnbEnvInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AMD_ENV_PARAMS *EnvParamsPtr;
UINT32 Property;
GNB_HANDLE *GnbHandle;
D18F5x170_STRUCT D18F5x170;
D0F0xBC_x1F8DC_STRUCT D0F0xBC_x1F8DC;
PP_FUSE_ARRAY *PpFuseArray;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n");
Property = TABLE_PROPERTY_DEFAULT;
EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
GnbHandle = GnbGetHandle (StdHeader);
ASSERT (GnbHandle != NULL);
GnbLoadFuseTableTN (StdHeader);
Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader);
GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader);
GnbClumpUnitIdV4 (GnbHandle, StdHeader);
GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader);
Property |= GnbBuildOptionsTN.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0;
if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) {
Property |= TABLE_PROPERTY_IOMMU_DISABLED;
} else {
// Force disable iommu if non-FM2
// PACKAGE_TYPE_FP2 1
// PACKAGE_TYPE_FS1r2 2
// PACKAGE_TYPE_FM2 4
if (LibAmdGetPackageType (StdHeader) != PACKAGE_TYPE_FM2) {
EnvParamsPtr->GnbEnvConfiguration.IommuSupport = FALSE;
Property |= TABLE_PROPERTY_IOMMU_DISABLED;
} else {
Property |= GnbBuildOptionsTN.GnbCommonOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0;
Property |= GnbBuildOptionsTN.GnbCommonOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0;
}
}
if (GnbBuildOptionsTN.CfgNbdpmEnable) {
GnbRegisterReadTN (
TYPE_D18F5,
D18F5x170_ADDRESS,
&D18F5x170.Value,
0,
StdHeader
);
// Check if NbPstate enable
if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) {
Property |= TABLE_PROPERTY_NBDPM;
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
// NBDPM is requesting SclkVid0 from the register.
// Write them back if SclkVid has been changed in PpFuseArray.
GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader);
if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) ||
(D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) ||
(D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) ||
(D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) {
D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0];
D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1];
D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2];
D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3];
GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
}
}
}
IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEnvInitTableTN,
Property,
GNB_TABLE_FLAGS_FORCE_S3_SAVE,
StdHeader
);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status);
return Status;
}
