static int TTransform(const uint8_t* in, const uint16_t* w) {
int sum;
uint32_t in0_m, in1_m, in2_m, in3_m;
v16i8 src0;
v8i16 in0, in1, tmp0, tmp1, tmp2, tmp3;
v4i32 dst0, dst1;
const v16i8 zero = { 0 };
const v8i16 mask0 = { 0, 1, 2, 3, 8, 9, 10, 11 };
const v8i16 mask1 = { 4, 5, 6, 7, 12, 13, 14, 15 };
const v8i16 mask2 = { 0, 4, 8, 12, 1, 5, 9, 13 };
const v8i16 mask3 = { 3, 7, 11, 15, 2, 6, 10, 14 };
LW4(in, BPS, in0_m, in1_m, in2_m, in3_m);
INSERT_W4_SB(in0_m, in1_m, in2_m, in3_m, src0);
ILVRL_B2_SH(zero, src0, tmp0, tmp1);
VSHF_H2_SH(tmp0, tmp1, tmp0, tmp1, mask2, mask3, in0, in1);
ADDSUB2(in0, in1, tmp0, tmp1);
VSHF_H2_SH(tmp0, tmp1, tmp0, tmp1, mask0, mask1, tmp2, tmp3);
ADDSUB2(tmp2, tmp3, tmp0, tmp1);
VSHF_H2_SH(tmp0, tmp1, tmp0, tmp1, mask2, mask3, in0, in1);
ADDSUB2(in0, in1, tmp0, tmp1);
VSHF_H2_SH(tmp0, tmp1, tmp0, tmp1, mask0, mask1, tmp2, tmp3);
ADDSUB2(tmp2, tmp3, tmp0, tmp1);
tmp0 = __msa_add_a_h(tmp0, (v8i16)zero);
tmp1 = __msa_add_a_h(tmp1, (v8i16)zero);
LD_SH2(w, 8, tmp2, tmp3);
DOTP_SH2_SW(tmp0, tmp1, tmp2, tmp3, dst0, dst1);
dst0 = dst0 + dst1;
sum = HADD_SW_S32(dst0);
return sum;
}
void vpx_fdct8x8_1_msa(const int16_t *input, int16_t *out, int32_t stride) {
v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
v4i32 vec_w;
LD_SH8(input, stride, in0, in1, in2, in3, in4, in5, in6, in7);
ADD4(in0, in1, in2, in3, in4, in5, in6, in7, in0, in2, in4, in6);
ADD2(in0, in2, in4, in6, in0, in4);
vec_w = __msa_hadd_s_w(in0, in0);
vec_w += __msa_hadd_s_w(in4, in4);
out[0] = HADD_SW_S32(vec_w);
out[1] = 0;
}
static int32_t avc_quant_4x4_msa( int16_t *p_dct, uint16_t *p_mf,
uint16_t *p_bias )
{
int32_t non_zero = 0;
v8i16 dct0, dct1;
v8i16 zero = { 0 };
v8i16 dct0_mask, dct1_mask;
v8i16 dct_h0, dct_h1, mf_h0, mf_h1, bias_h0, bias_h1;
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 dct_w0, dct_w1, dct_w2, dct_w3;
v4i32 mf_vec0, mf_vec1, mf_vec2, mf_vec3;
v4i32 bias0, bias1, bias2, bias3;
LD_SH2( p_dct, 8, dct0, dct1 );
LD_SH2( p_bias, 8, bias_h0, bias_h1 );
LD_SH2( p_mf, 8, mf_h0, mf_h1 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
ILVR_H2_SW( zero, bias_h0, zero, bias_h1, bias0, bias2 );
ILVL_H2_SW( zero, bias_h0, zero, bias_h1, bias1, bias3 );
ILVR_H2_SW( zero, mf_h0, zero, mf_h1, mf_vec0, mf_vec2 );
ILVL_H2_SW( zero, mf_h0, zero, mf_h1, mf_vec1, mf_vec3 );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias1 );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias0 );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias2 );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias3 );
dct_w0 *= mf_vec0;
dct_w1 *= mf_vec1;
dct_w2 *= mf_vec2;
dct_w3 *= mf_vec3;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
PCKEV_H2_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_h0, dct_h1 );
dct0 = zero - dct_h0;
dct1 = zero - dct_h1;
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0, ( v16u8 ) dct0,
( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1, ( v16u8 ) dct1,
( v16u8 ) dct1_mask );
non_zero = HADD_SW_S32( ( v4u32 ) ( dct_h0 + dct_h1 ) );
ST_SH2( dct0, dct1, p_dct, 8 );
return !!non_zero;
}
static int32_t avc_quant_4x4_dc_msa( int16_t *p_dct, int32_t i_mf,
int32_t i_bias )
{
int32_t non_zero = 0;
v8i16 dct0, dct1, dct0_mask, dct1_mask;
v8i16 zero = { 0 };
v8i16 dct_h0, dct_h1;
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 dct_w0, dct_w1, dct_w2, dct_w3;
v4i32 mf_vec, bias_vec;
LD_SH2( p_dct, 8, dct0, dct1 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
bias_vec = __msa_fill_w( i_bias );
mf_vec = __msa_fill_w( i_mf );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias_vec );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias_vec );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias_vec );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias_vec );
dct_w0 *= mf_vec;
dct_w1 *= mf_vec;
dct_w2 *= mf_vec;
dct_w3 *= mf_vec;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
PCKEV_H2_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_h0, dct_h1 );
dct0 = zero - dct_h0;
dct1 = zero - dct_h1;
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0,
( v16u8 ) dct0, ( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1,
( v16u8 ) dct1, ( v16u8 ) dct1_mask );
non_zero = HADD_SW_S32( ( v4u32 ) ( dct_h0 + dct_h1 ) );
ST_SH2( dct0, dct1, p_dct, 8 );
return !!non_zero;
}
void vpx_fdct16x16_1_msa(const int16_t *input, int16_t *out, int32_t stride) {
int sum, i;
v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
v4i32 vec_w = { 0 };
for (i = 0; i < 4; ++i) {
LD_SH2(input, 8, in0, in1);
input += stride;
LD_SH2(input, 8, in2, in3);
input += stride;
LD_SH2(input, 8, in4, in5);
input += stride;
LD_SH2(input, 8, in6, in7);
input += stride;
ADD4(in0, in1, in2, in3, in4, in5, in6, in7, in0, in2, in4, in6);
ADD2(in0, in2, in4, in6, in0, in4);
vec_w += __msa_hadd_s_w(in0, in0);
vec_w += __msa_hadd_s_w(in4, in4);
}
sum = HADD_SW_S32(vec_w);
out[0] = (int16_t)(sum >> 1);
}
static int32_t avc_quant_8x8_msa( int16_t *p_dct, uint16_t *p_mf,
uint16_t *p_bias )
{
int32_t non_zero = 0;
v8i16 dct0, dct1, dct2, dct3;
v8i16 zero = { 0 };
v8i16 dct0_mask, dct1_mask, dct2_mask, dct3_mask;
v8i16 dct_h0, dct_h1, dct_h2, dct_h3, mf_h0, mf_h1, mf_h2, mf_h3;
v8i16 bias_h0, bias_h1, bias_h2, bias_h3;
v4i32 dct_w0, dct_w1, dct_w2, dct_w3, dct_w4, dct_w5, dct_w6, dct_w7;
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 dct_signed_w4, dct_signed_w5, dct_signed_w6, dct_signed_w7;
v4i32 mf_vec0, mf_vec1, mf_vec2, mf_vec3;
v4i32 mf_vec4, mf_vec5, mf_vec6, mf_vec7;
v4i32 bias0, bias1, bias2, bias3, bias4, bias5, bias6, bias7;
LD_SH4( p_dct, 8, dct0, dct1, dct2, dct3 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
dct2_mask = __msa_clei_s_h( dct2, 0 );
dct3_mask = __msa_clei_s_h( dct3, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
UNPCK_SH_SW( dct2, dct_signed_w4, dct_signed_w5 );
UNPCK_SH_SW( dct3, dct_signed_w6, dct_signed_w7 );
LD_SH4( p_bias, 8, bias_h0, bias_h1, bias_h2, bias_h3 );
ILVR_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias0, bias2, bias4, bias6 );
ILVL_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias1, bias3, bias5, bias7 );
LD_SH4( p_mf, 8, mf_h0, mf_h1, mf_h2, mf_h3 );
ILVR_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec0, mf_vec2, mf_vec4, mf_vec6 );
ILVL_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec1, mf_vec3, mf_vec5, mf_vec7 );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias0 );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias1 );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias2 );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias3 );
dct_w4 = __msa_add_a_w( dct_signed_w4, bias4 );
dct_w5 = __msa_add_a_w( dct_signed_w5, bias5 );
dct_w6 = __msa_add_a_w( dct_signed_w6, bias6 );
dct_w7 = __msa_add_a_w( dct_signed_w7, bias7 );
dct_w0 *= mf_vec0;
dct_w1 *= mf_vec1;
dct_w2 *= mf_vec2;
dct_w3 *= mf_vec3;
dct_w4 *= mf_vec4;
dct_w5 *= mf_vec5;
dct_w6 *= mf_vec6;
dct_w7 *= mf_vec7;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
SRA_4V( dct_w4, dct_w5, dct_w6, dct_w7, 16 );
PCKEV_H4_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_w5, dct_w4, dct_w7, dct_w6,
dct_h0, dct_h1, dct_h2, dct_h3 );
SUB4( zero, dct_h0, zero, dct_h1, zero, dct_h2, zero, dct_h3,
dct0, dct1, dct2, dct3 );
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0,
( v16u8 ) dct0, ( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1,
( v16u8 ) dct1, ( v16u8 ) dct1_mask );
dct2 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h2,
( v16u8 ) dct2, ( v16u8 ) dct2_mask );
dct3 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h3,
( v16u8 ) dct3, ( v16u8 ) dct3_mask );
non_zero = HADD_SW_S32( ( v4u32 )( dct_h0 + dct_h1 + dct_h2 + dct_h3 ) );
ST_SH4( dct0, dct1, dct2, dct3, p_dct, 8 );
LD_SH4( p_dct + 32, 8, dct0, dct1, dct2, dct3 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
dct2_mask = __msa_clei_s_h( dct2, 0 );
dct3_mask = __msa_clei_s_h( dct3, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
UNPCK_SH_SW( dct2, dct_signed_w4, dct_signed_w5 );
UNPCK_SH_SW( dct3, dct_signed_w6, dct_signed_w7 );
LD_SH4( p_bias + 32, 8, bias_h0, bias_h1, bias_h2, bias_h3 );
ILVR_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias0, bias2, bias4, bias6 );
ILVL_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias1, bias3, bias5, bias7 );
LD_SH4( p_mf + 32, 8, mf_h0, mf_h1, mf_h2, mf_h3 );
ILVR_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec0, mf_vec2, mf_vec4, mf_vec6 );
ILVL_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec1, mf_vec3, mf_vec5, mf_vec7 );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias0 );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias1 );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias2 );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias3 );
dct_w4 = __msa_add_a_w( dct_signed_w4, bias4 );
dct_w5 = __msa_add_a_w( dct_signed_w5, bias5 );
dct_w6 = __msa_add_a_w( dct_signed_w6, bias6 );
dct_w7 = __msa_add_a_w( dct_signed_w7, bias7 );
dct_w0 *= mf_vec0;
dct_w1 *= mf_vec1;
dct_w2 *= mf_vec2;
dct_w3 *= mf_vec3;
dct_w4 *= mf_vec4;
dct_w5 *= mf_vec5;
dct_w6 *= mf_vec6;
dct_w7 *= mf_vec7;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
SRA_4V( dct_w4, dct_w5, dct_w6, dct_w7, 16 );
PCKEV_H2_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_h0, dct_h1 );
PCKEV_H2_SH( dct_w5, dct_w4, dct_w7, dct_w6, dct_h2, dct_h3 );
SUB4( zero, dct_h0, zero, dct_h1, zero, dct_h2, zero, dct_h3,
dct0, dct1, dct2, dct3 );
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0,
( v16u8 ) dct0, ( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1,
( v16u8 ) dct1, ( v16u8 ) dct1_mask );
dct2 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h2,
( v16u8 ) dct2, ( v16u8 ) dct2_mask );
dct3 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h3,
( v16u8 ) dct3, ( v16u8 ) dct3_mask );
non_zero += HADD_SW_S32( ( v4u32 ) ( dct_h0 + dct_h1 + dct_h2 + dct_h3 ) );
ST_SH4( dct0, dct1, dct2, dct3, p_dct + 32, 8 );
return !!non_zero;
}
