externC void
_mb93091_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
{
cyg_uint32 cfg_addr, addr, status;
if (!_mb93091_has_vdk)
return;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _MB93091_PCI_CONFIG + ((offset << 1) ^ 0x02);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
addr = _MB93091_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
}
HAL_WRITE_UINT16(addr, cfg_val);
HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
if (status & _MB93091_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
}
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
}
void
cyg_hal_plf_scif_init_channel(channel_data_t* chan)
{
cyg_uint8* base = chan->base;
cyg_uint8 tmp;
cyg_uint16 sr;
int baud_rate = CYGNUM_HAL_SH_SH2_SCIF_BAUD_RATE;
// Disable everything.
HAL_WRITE_UINT8(base+_REG_SCSCR, 0);
// Reset FIFO.
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
HAL_WRITE_UINT16(base+_REG_SCFER, 0);
// 8-1-no parity. This is also fine for IrDA mode
HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
if (chan->irda_mode)
HAL_WRITE_UINT8(base+_REG_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD);
else {
HAL_WRITE_UINT8(base+_REG_SCIMR, 0);
}
// Set speed to CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE
HAL_READ_UINT8(base+_REG_SCSMR, tmp);
tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
tmp |= CYGARC_SCBRR_CKSx(baud_rate);
HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(baud_rate));
// Let things settle: Here we should should wait the equivalent of
// one bit interval,
// i.e. 1/CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE second, but
// until we have something like the Linux delay loop, it's hard to
// do reliably. So just move on and hope for the best (this is
// unlikely to cause problems since the CPU has just come out of
// reset anyway).
// Clear status register (read back first).
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR, 0);
HAL_WRITE_UINT8(base+_REG_SC2SSR, CYGARC_REG_SCIF_SC2SSR_BITRATE_16|CYGARC_REG_SCIF_SC2SSR_EI);
// Bring FIFO out of reset and set to trigger on every char in
// FIFO (or C-c input would not be processed).
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);
// Leave Tx/Rx interrupts disabled, but enable Rx/Tx (only Rx for IrDA)
if (chan->irda_mode)
HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
else if (chan->async_rxtx_mode)
HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
#endif
else
HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
}
void
cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint16 fdr, sr;
cyg_uint8 scscr = 0;
CYGARC_HAL_SAVE_GP();
HAL_READ_UINT8(base+_REG_SCSCR, scscr);
if (chan->irda_mode) {
HAL_WRITE_UINT8(base+_REG_SCSCR, scscr|CYGARC_REG_SCIF_SCSCR_TE);
}
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
if (chan->async_rxtx_mode) {
HAL_WRITE_UINT8(base+_REG_SCSCR, (scscr|CYGARC_REG_SCIF_SCSCR_TE)&~CYGARC_REG_SCIF_SCSCR_RE);
}
#endif
do {
HAL_READ_UINT16(base+_REG_SCFDR, fdr);
} while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16);
HAL_WRITE_UINT8(base+_REG_SCFTDR, c);
// Clear FIFO-empty/transmit end flags (read back SR first)
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK
& ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND ));
// Hang around until all characters have been safely sent.
do {
HAL_READ_UINT16(base+_REG_SCSSR, sr);
} while ((sr & CYGARC_REG_SCIF_SCSSR_TEND) == 0);
if (chan->irda_mode) {
#ifdef CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
// In IrDA mode there will be generated spurious RX events when
// the TX unit is switched on. Eat that character.
cyg_uint8 _junk;
HAL_READ_UINT8(base+_REG_SCFRDR, _junk);
// Clear buffer full flag (read back first)
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR,
CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR));
#endif // CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
// Disable transmitter again
HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
}
#ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
if (chan->async_rxtx_mode) {
// Disable transmitter, enable receiver
HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
}
#endif // CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
CYGARC_HAL_RESTORE_GP();
}
//==========================================================================
// Initialize driver & hardware state
//==========================================================================
void cyg_lpc2xxx_i2c_init(struct cyg_i2c_bus *bus)
{
cyg_lpc2xxx_i2c_extra* extra = (cyg_lpc2xxx_i2c_extra*)bus->i2c_extra;
cyg_uint16 duty_cycle;
cyg_drv_mutex_init(&extra->i2c_lock);
cyg_drv_cond_init(&extra->i2c_wait, &extra->i2c_lock);
cyg_drv_interrupt_create(I2C_ISRVEC(extra),
I2C_ISRPRI(extra),
(cyg_addrword_t) extra,
&lpc2xxx_i2c_isr,
&lpc2xxx_i2c_dsr,
&(extra->i2c_interrupt_handle),
&(extra->i2c_interrupt_data));
cyg_drv_interrupt_attach(extra->i2c_interrupt_handle);
CLR_CON(extra, CON_EN | CON_STA | CON_SI | CON_AA);
HAL_WRITE_UINT8(I2C_ADR(extra), 0);
//
// Setup I2C bus frequency
//
duty_cycle = (I2C_CLK(extra) / I2C_BUS_FREQ(extra)) / 2;
HAL_WRITE_UINT16(I2C_SCLL(extra), duty_cycle);
HAL_WRITE_UINT16(I2C_SCLH(extra), duty_cycle);
SET_CON(extra, CON_EN);
}
//static
cyg_bool
cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint16 fdr, sr;
cyg_bool res = false;
HAL_READ_UINT16(base+_REG_SCSSR, sr);
if (sr & CYGARC_REG_SCIF_SCSSR_ER) {
cyg_uint8 ssr2;
HAL_WRITE_UINT16(base+_REG_SCFER, 0);
HAL_READ_UINT8(base+_REG_SC2SSR, ssr2);
ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER;
HAL_WRITE_UINT8(base+_REG_SC2SSR, ssr2);
HAL_WRITE_UINT16(base+_REG_SCSSR,
CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_BRK | CYGARC_REG_SCIF_SCSSR_FER | CYGARC_REG_SCIF_SCSSR_PER));
}
HAL_READ_UINT16(base+_REG_SCFDR, fdr);
if (0 != (fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK)) {
HAL_READ_UINT8(base+_REG_SCFRDR, *ch);
// Clear DR/RDF flags
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR,
CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF | CYGARC_REG_SCIF_SCSSR_DR));
res = true;
}
return res;
}
//-----------------------------------------------------------------------------
static void
init_serial_channel(const channel_data_t* __ch_data)
{
cyg_uint16 * base = __ch_data->base;
cyg_uint16 br;
switch(__ch_data->baud_rate)
{
case 300:
br = CYG_DEV_SERIAL_RS232_SCxBR_300;
break;
case 600:
br = CYG_DEV_SERIAL_RS232_SCxBR_600;
break;
case 1200:
br = CYG_DEV_SERIAL_RS232_SCxBR_1200;
break;
case 2400:
br = CYG_DEV_SERIAL_RS232_SCxBR_2400;
break;
case 4800:
br = CYG_DEV_SERIAL_RS232_SCxBR_4800;
break;
case 9600:
br = CYG_DEV_SERIAL_RS232_SCxBR_9600;
break;
case 14400:
br = CYG_DEV_SERIAL_RS232_SCxBR_14400;
break;
case 19200:
br = CYG_DEV_SERIAL_RS232_SCxBR_19200;
break;
case 28800:
br = CYG_DEV_SERIAL_RS232_SCxBR_28800;
break;
case 38400:
br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
break;
case 57600:
br = CYG_DEV_SERIAL_RS232_SCxBR_57600;
break;
case 115200:
br = CYG_DEV_SERIAL_RS232_SCxBR_115200;
break;
default:
// Use the default if something unknown is requested
br = CYG_DEV_SERIAL_RS232_SCxBR_38400;
break;
}
// 8-1-No parity, enable transmitter and receiver, leave interrupts
// as they are
HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, (SCCR1_TE | SCCR1_RE));
// Set baud rate
HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR0, br);
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint16 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg |= FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg &= ~(cyg_uint16)FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
void cyg_hal_plf_pci_init(void)
{
int i;
cyg_uint32 val;
#if 0
char idbuf[16];
for(i=0; i<16; i++)
HAL_READ_UINT8(GAPSPCI_REGS+i, idbuf[i]);
if(strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
return;
#endif
gapspci_initialized = false;
HAL_WRITE_UINT32(GAPSPCI_REGS+0x18, 0x5a14a501);
for(i=0; i<1000000; i++);
HAL_READ_UINT32(GAPSPCI_REGS+0x18, val);
if (val != 1) return;
HAL_WRITE_UINT32(GAPSPCI_REGS+0x20, 0x01000000);
HAL_WRITE_UINT32(GAPSPCI_REGS+0x24, 0x01000000);
HAL_WRITE_UINT32(GAPSPCI_REGS+0x28, GAPSPCI_DMA_BASE);
HAL_WRITE_UINT32(GAPSPCI_REGS+0x2c, GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE);
HAL_WRITE_UINT32(GAPSPCI_REGS+0x14, 1);
HAL_WRITE_UINT32(GAPSPCI_REGS+0x34, 1);
#if 1
/* Setting up Broadband Adapter */
HAL_WRITE_UINT16(GAPSPCI_BBA_CONFIG+0x06, 0xf900);
HAL_WRITE_UINT32(GAPSPCI_BBA_CONFIG+0x30, 0x00000000);
HAL_WRITE_UINT8 (GAPSPCI_BBA_CONFIG+0x3c, 0x00);
HAL_WRITE_UINT8 (GAPSPCI_BBA_CONFIG+0x0d, 0xf0);
HAL_WRITE_UINT16(GAPSPCI_BBA_CONFIG+0x04, 0x0006);
HAL_WRITE_UINT32(GAPSPCI_BBA_CONFIG+0x10, 0x00002001);
HAL_WRITE_UINT32(GAPSPCI_BBA_CONFIG+0x14, 0x01000000);
#endif
/* Enable interrupt */
HAL_READ_UINT32(GAPSPCI_INTC, val);
val |= (1<<3);
HAL_WRITE_UINT32(GAPSPCI_INTC, val);
gapspci_initialized = true;
}
externC cyg_uint32
_mb93091_pci_cfg_read_uint32(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr, addr, status;
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
if (!_mb93091_has_vdk)
return cfg_val;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _MB93091_PCI_CONFIG + (offset << 1);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset);
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, cfg_addr);
addr = _MB93091_PCI_CONFIG_DATA;
}
HAL_READ_UINT32(addr, cfg_val);
HAL_READ_UINT16(_MB93091_PCI_STAT_CMD, status);
if (status & _MB93091_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
cfg_val = (cyg_uint32)0xFFFFFFFF;
HAL_WRITE_UINT16(_MB93091_PCI_STAT_CMD, status & _MB93091_PCI_STAT_ERROR_MASK);
}
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
HAL_WRITE_UINT32(_MB93091_PCI_CONFIG_ADDR, 0);
return cfg_val;
}
void
cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint16 fdr, sr;
CYGARC_HAL_SAVE_GP();
do {
HAL_READ_UINT16(base+_REG_SCFDR, fdr);
} while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16);
HAL_WRITE_UINT8(base+_REG_SCFTDR, c);
// Clear FIFO-empty/transmit end flags (read back SR first)
HAL_READ_UINT16(base+_REG_SCFSR, sr);
HAL_WRITE_UINT16(base+_REG_SCFSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK
& ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND ));
// Hang around until the character has been safely sent.
do {
HAL_READ_UINT16(base+_REG_SCFDR, fdr);
} while ((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) != 0);
CYGARC_HAL_RESTORE_GP();
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
CYG_ADDRESS esci_base = (CYG_ADDRESS) chan->base;
cyg_uint16 esci_sr;
int res = 0;
cyg_uint8 ch_in;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr);
if (esci_sr & FREESCALE_ESCI_SR_RDRF) {
HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in);
if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF);
}
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
cyg_uint8 c;
cyg_uint16 fdr, sr;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
int res = 0;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT16(base+_REG_SCFDR, fdr);
if ((fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK) != 0) {
HAL_READ_UINT8(base+_REG_SCFRDR, c);
// Clear buffer full flag (read back first).
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR,
CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_RDF);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
int
hal_enable_profile_timer(int resolution)
{
// Run periodic timer interrupt for profile
cyg_uint16 piscr;
int period = resolution / 100;
// Attach pit arbiter.
HAL_INTERRUPT_ATTACH (PIT_IRQ,
&hal_arbitration_isr_pit, ID_PIT, 0);
HAL_INTERRUPT_UNMASK (PIT_IRQ);
// Attach pit isr.
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit,
ID_PIT, 0);
HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, PIT_IRQ_LEVEL);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
// Set period.
HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC,
(2*period) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);
// Enable.
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr |= CYGARC_REG_IMM_PISCR_PTE;
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
return resolution;
}
externC cyg_uint32
_csb281_pci_cfg_read_uint32(int bus, int devfn, int offset)
{
cyg_uint32 addr;
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
addr = _cfg_sel(bus, devfn, offset);
HAL_READ_UINT32LE(addr, cfg_val);
#if 0
HAL_READ_UINT16(_CSB281_PCI_STAT_CMD, status);
if (status & _CSB281_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
cfg_val = (cyg_uint32)0xFFFFFFFF;
HAL_WRITE_UINT16(_CSB281_PCI_STAT_CMD, status & _CSB281_PCI_STAT_ERROR_MASK);
}
#endif
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
HAL_WRITE_UINT32(_CSB281_PCI_CONFIG_ADDR, 0);
return cfg_val;
}
void
cyg_hal_sh_pcic_pci_io_write_word (cyg_uint32 addr, cyg_uint16 data)
{
HAL_WRITE_UINT32(CYGARC_REG_PCIC_IOBR, addr & CYGARC_REG_PCIC_IOBR_MASK);
HAL_WRITE_UINT16(CYGARC_REG_PCIC_IO_BASE + (addr & CYGARC_REG_PCIC_IO_BASE_MASK),
data);
}
static void
mn10300_serial_stop_xmit(serial_channel *chan)
{
#ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE
mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv;
cyg_uint16 cr;
cyg_uint16 sr;
// Wait until the transmitter has actually stopped before turning it off.
do
{
sr = mn10300_read_sr( mn10300_chan );
} while( sr & SR_TXF );
HAL_READ_UINT16( mn10300_chan->base+SERIAL_CTR, cr );
DISABLE_TRANSMIT_INTERRUPT(mn10300_chan);
HAL_WRITE_UINT16( mn10300_chan->base+SERIAL_CTR, cr );
cyg_drv_interrupt_mask(mn10300_chan->tx_int);
#endif
}
// Initialize SDRAM controller
void plf_init_sdramc(void)
{
cyg_uint16 sdcr;
HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr);
// Do not initialize SDRAM if it is already active
if (!(sdcr & MCF5272_SDRAMC_SDCCR_ACT))
{
#if (CYGHWR_HAL_SYSTEM_CLOCK_MHZ == 66)
HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0
| MCF5272_SDRAMC_SDCTR_RTP_66MHz
| MCF5272_SDRAMC_SDCTR_RC(0)
| MCF5272_SDRAMC_SDCTR_RP(1)
| MCF5272_SDRAMC_SDCTR_RCD(1)
| MCF5272_SDRAMC_SDCTR_CLT_2));
#else
// Clock frequency must be 48 Mhz
HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdtr, (0
| MCF5272_SDRAMC_SDCTR_RTP_48MHz
| MCF5272_SDRAMC_SDCTR_RC(0)
| MCF5272_SDRAMC_SDCTR_RP(1)
| MCF5272_SDRAMC_SDCTR_RCD(0)
| MCF5272_SDRAMC_SDCTR_CLT_2));
#endif
HAL_WRITE_UINT16(&MCF5272_DEVS->sdramc.sdcr, (0
| MCF5272_SDRAMC_SDCCR_MCAS_A9
#if (CYGHWR_INSTALLED_SDRAM_SIZE == 4)
| MCF5272_SDRAMC_SDCCR_BALOC_A21
#else
| MCF5272_SDRAMC_SDCCR_BALOC_A22
#endif
| MCF5272_SDRAMC_SDCCR_REG
| MCF5272_SDRAMC_SDCCR_INIT));
// Start SDRAM controller with a memory write
*((volatile char *) CYGMEM_REGION_sdram) = 0;
// Wait until controller is ready
do
{
HAL_READ_UINT16(&MCF5272_DEVS->sdramc.sdcr, sdcr);
} while(!(sdcr & MCF5272_SDRAMC_SDCCR_ACT));
}
}
// Write one datum to 16-bit bus
static int write_data_16(struct dm9000 *p, cyg_uint8 *src)
{
cyg_uint16 val;
memcpy(&val, src, 2);
HAL_WRITE_UINT16(p->io_data, val);
return 2;
}
void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint16 val)
{
if (gapspci_initialized && BBA_SELECTED(bus, devfn))
HAL_WRITE_UINT16(GAPSPCI_BBA_CONFIG+offset, val);
}
static void cyg_hal_plf_serial_set_baudrate_internal(cyg_uint8 port, int baudrate){
float n, nn;
int t, tt;
n = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) (32 * baudrate) - 1;
nn = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) (32 * baudrate) - 1.5;
/* rounding */
t = n;
tt = nn;
if ( (n-t) > (1 - (n-t)) ) t++;
if ( (nn-tt) > (1 - (nn-tt)) ) tt++;
/* check which is better t or tt */
/* back calculation of baudrate from t and tt */
n = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) ((2*t+2) * 16);
nn = (CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ * 1000000 / CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER) / (float) ((2*tt+3) * 16);
/* taking difference between wanted baudrate and back calculated br */
if ((baudrate - n) < 0)
n = n - baudrate;
else
n = baudrate - n;
if ((baudrate - nn) < 0)
nn = nn - baudrate;
else
nn = baudrate - nn;
/* and finally take the best */
if (n < nn){
/* UCC1 = 0 */
HAL_WRITE_UINT16(port + CYG_HAL_FR30_MB91301_UTIMR_OFFSET, t);
HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_UTIMC_OFFSET, 0x02);
} else {
/* UCC1 = 1 */
HAL_WRITE_UINT16(port + CYG_HAL_FR30_MB91301_UTIMR_OFFSET, tt);
HAL_WRITE_UINT8(port + CYG_HAL_FR30_MB91301_UTIMC_OFFSET, 0x82);
}
}
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 *esci_base = chan->base;
// Reset device
// 8-1-no parity.
HAL_WRITE_UINT8(FREESCALE_ESCI_CR3(esci_base), 0);
HAL_WRITE_UINT16(FREESCALE_ESCI_LINCTRL(esci_base), 0);
HAL_WRITE_UINT16(FREESCALE_ESCI_BD(esci_base),
FREESCALE_ESCI_BAUD(chan->baud_rate));
// Enable RX and TX
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(esci_base), (FREESCALE_ESCI_CR12_TE |
FREESCALE_ESCI_CR12_RE));
}
void
hal_mace1_led_off(int val)
{
cyg_uint16 leds;
// read old LED state
HAL_READ_UINT16(MAC7100_PIM_PORTDATA(MAC7100_PORT_A_OFFSET), leds);
leds&=~(1<<(8+val));
// Write new state
HAL_WRITE_UINT16(MAC7100_PIM_PORTDATA(MAC7100_PORT_A_OFFSET), leds);
}
// Note: The PINTs can be masked and configured individually, even
// though there are only two vectors. Maybe add some fake vectors just
// for masking/configuring?
void
hal_interrupt_configure(int vector, int level, int up)
{
#if (CYGARC_SH_MOD_INTC >= 2)
if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
&& (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
cyg_uint16 icr1, ss, mask;
ss = 0;
mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL;
if (up) ss |= CYGARC_REG_ICR1_SENSE_UP;
if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL;
CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
switch( (vector) ) {
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
break;
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
break;
#endif
default:
CYG_FAIL("Unhandled interrupt vector");
}
HAL_READ_UINT16(CYGARC_REG_ICR1, icr1);
icr1 &= ~mask;
icr1 |= ss;
HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1);
}
#endif
CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vector, level, up);
}
void
do_iopoke(int argc, char *argv[])
{
struct option_info opts[5];
unsigned long base;
bool base_set, value_set;
bool set_32bit = false;
bool set_16bit = false;
bool set_8bit = false;
cyg_uint32 value;
int size = 1;
init_opts(&opts[0], 'b', true, OPTION_ARG_TYPE_NUM,
&base, &base_set, "base address");
init_opts(&opts[1], 'v', true, OPTION_ARG_TYPE_NUM,
&value, &value_set, "valuex");
init_opts(&opts[2], '4', false, OPTION_ARG_TYPE_FLG,
&set_32bit, 0, "output 32 bit units");
init_opts(&opts[3], '2', false, OPTION_ARG_TYPE_FLG,
&set_16bit, 0, "output 16 bit units");
init_opts(&opts[4], '1', false, OPTION_ARG_TYPE_FLG,
&set_8bit, 0, "output 8 bit units");
if (!scan_opts(argc, argv, 1, opts, 5, 0, 0, "")) {
return;
}
if (!base_set) {
diag_printf("iopoke what <location>?\n");
return;
}
if (!value_set) {
diag_printf("iopoke what <value>?\n");
return;
}
if (set_32bit) {
size = 4;
} else if (set_16bit) {
size = 2;
} else if (set_8bit) {
size = 1;
}
switch (size) {
case 4:
HAL_WRITE_UINT32 ( base, value );
break;
case 2:
HAL_WRITE_UINT16 ( base, value );
break;
case 1:
HAL_WRITE_UINT8 ( base, value );
break;
}
}
int
hal_enable_profile_timer(int resolution)
{
cyg_uint16 ticks;
// Make sure the clock is not running but is otherwise initialized.
HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR,
HAL_MCFxxxx_PITx_PCSR_PRE_64 | HAL_MCFxxxx_PITx_PCSR_OVW |
HAL_MCFxxxx_PITx_PCSR_PIE | HAL_MCFxxxx_PITx_PCSR_PIF |
HAL_MCFxxxx_PITx_PCSR_RLD);
// The resolution is a time interval in microseconds. The actual
// cpu clock frequency is determined by the platform. This is divided
// by 64, which means it may not be possible to get the exact resolution.
ticks = ((resolution * CYGHWR_HAL_SYSTEM_CLOCK_MHZ) / 64) - 1;
HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PMR, ticks);
// Convert back to microseconds. This may actually increase rounding
// errors for some arguments and platforms, but the result should
// still be accurate enough for practical purposes.
resolution = ((ticks + 1) * 64) / CYGHWR_HAL_SYSTEM_CLOCK_MHZ;
// Set up the interrupt handler. This is usually a high-priority
// interrupt so that we can get profiling information for other
// interrupt sources.
#ifdef HAL_VSR_SET
HAL_VSR_SET(HAL_MCFxxxx_PROFILE_TIMER_VECTOR, &hal_mcfxxxx_profile_vsr, (cyg_uint32)0);
#endif
HAL_INTERRUPT_SET_LEVEL(HAL_MCFxxxx_PROFILE_TIMER_ISR, CYGNUM_HAL_M68K_MCFxxxx_SOFTWARE_PROFILE_TIMER_ISR_PRIORITY);
HAL_INTERRUPT_UNMASK(HAL_MCFxxxx_PROFILE_TIMER_ISR);
// Now start the timer running.
HAL_WRITE_UINT16(HAL_MCFxxxx_PROFILE_TIMER_BASE + HAL_MCFxxxx_PITx_PCSR,
HAL_MCFxxxx_PITx_PCSR_PRE_64 | HAL_MCFxxxx_PITx_PCSR_OVW |
HAL_MCFxxxx_PITx_PCSR_PIE | HAL_MCFxxxx_PITx_PCSR_PIF |
HAL_MCFxxxx_PITx_PCSR_RLD | HAL_MCFxxxx_PITx_PCSR_EN);
// Return the actual resolution.
return resolution;
}
void
cyg_hal_plf_scif_init_channel(channel_data_t* chan)
{
cyg_uint8* base = chan->base;
cyg_uint16 sr;
// Disable everything.
HAL_WRITE_UINT16(base+_REG_SCSCR, 0);
// Reset FIFO.
HAL_WRITE_UINT16(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
// 8-1-no parity.
HAL_WRITE_UINT16(base+_REG_SCSMR, 0);
chan->baud_rate = CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE;
cyg_hal_plf_scif_set_baud(base, CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE);
// Clear status register (read back first).
HAL_READ_UINT16(base+_REG_SCFSR, sr);
HAL_WRITE_UINT16(base+_REG_SCFSR, 0);
// Bring FIFO out of reset and set to trigger on every char in
// FIFO (or C-c input would not be processed).
HAL_WRITE_UINT16(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);
// Leave Tx/Rx interrupts disabled, but enable Tx/Rx
HAL_WRITE_UINT16(base+_REG_SCSCR,
CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
}
// Initialize SIM module and system configuration registers
void plf_init_sim(void)
{
// Set up the mapping of our internal registers. The LSB indicates that
// the register contents are valid.
CYGARC_MOVEC((CYG_WORD32)(CYGMEM_REGION_devs | 1), CYGARC_REG_MBAR);
// Initialize System Config Register
// Setup Watch Dog Timeout
HAL_WRITE_UINT16(&MCF5272_DEVS->cfg.scr, MCF5272_SIM_SCR_HWWD_1024);
// Initialize System Protection Register
// Enable all bus error exceptions
HAL_WRITE_UINT16(&MCF5272_DEVS->cfg.spr,
(0 | MCF5272_SIM_SPR_ADC | MCF5272_SIM_SPR_ADCEN
| MCF5272_SIM_SPR_WPV | MCF5272_SIM_SPR_WPVEN
| MCF5272_SIM_SPR_SMV | MCF5272_SIM_SPR_SMVEN
| MCF5272_SIM_SPR_SBE | MCF5272_SIM_SPR_SBEEN
| MCF5272_SIM_SPR_HWT | MCF5272_SIM_SPR_HWTEN
| MCF5272_SIM_SPR_RPV | MCF5272_SIM_SPR_RPVEN
| MCF5272_SIM_SPR_EXT | MCF5272_SIM_SPR_EXTEN
| MCF5272_SIM_SPR_SUV | MCF5272_SIM_SPR_SUVEN
)) ;
}
void
hal_mac7100_esci_pins(cyg_uint32 i_esci) {
cyg_uint16 *p_pim_config=0;
switch(i_esci) {
case FREESCALE_ESCI_A_I:
p_pim_config=
(cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,2);
break;
case FREESCALE_ESCI_B_I:
p_pim_config=(cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,0);
break;
case FREESCALE_ESCI_C_I:
p_pim_config=
(cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,14);
break;
case FREESCALE_ESCI_D_I:
p_pim_config=
(cyg_uint16 *)MAC7100_PIM_CONFIG(MAC7100_PORT_G_OFFSET,15);
break;
}
HAL_WRITE_UINT16(p_pim_config++, MAC7100_PIM_MODE_PERIPHERAL);
HAL_WRITE_UINT16(p_pim_config, MAC7100_PIM_MODE_PERIPHERAL);
}
// in:
//
// sym_type Type of relocation to apply,
// mem Address in memory to modify (relocate).
// sym_value
cyg_int32
cyg_ldr_relocate(cyg_int32 sym_type, cyg_uint32 mem, cyg_int32 sym_value)
{
cyg_int32 rel_offset, i;
// PPC uses rela, so we have to add the addend.
switch(sym_type)
{
case R_PPC_ADDR16_HA:
HAL_WRITE_UINT16(mem, _ha_(sym_value));
return 0;
case R_PPC_ADDR16_HI:
HAL_WRITE_UINT16(mem, _hi_(sym_value));
return 0;
case R_PPC_ADDR16_LO:
HAL_WRITE_UINT16(mem, _lo_(sym_value));
return 0;
case R_PPC_REL24:
// Now it is time to seek the destination address of the call.
// We need to do something in case the user jumps more than 16MB.
rel_offset = (sym_value - mem) & 0x03FFFFFC;
HAL_READ_UINT32(mem, i);
i &= 0xFC000003;
HAL_WRITE_UINT32(mem, rel_offset | i);
return 0;
case R_PPC_REL32:
HAL_WRITE_UINT32(mem, (sym_value - mem));
return 0;
case R_PPC_ADDR32:
HAL_WRITE_UINT32(mem, sym_value);
return 0;
default:
ELFDEBUG("FIXME: Unknown relocation value!!!\n");
return -1;
}
}
void
cyg_hal_plf_scif_init_channel(channel_data_t* chan)
{
cyg_uint8* base = chan->base;
cyg_uint8 tmp;
cyg_uint16 sr;
// Disable everything.
HAL_WRITE_UINT8(base+_REG_SCSCR, 0);
// Reset FIFO.
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
// 8-1-no parity.
HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
// Set speed to CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE
HAL_READ_UINT8(base+_REG_SCSMR, tmp);
tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE);
HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE));
// Let things settle: Here we should should wait the equivalent of
// one bit interval,
// i.e. 1/CYGNUM_HAL_SH_SH3_SCIF_DEFAULT_BAUD_RATE second, but
// until we have something like the Linux delay loop, it's hard to
// do reliably. So just move on and hope for the best (this is
// unlikely to cause problems since the CPU has just come out of
// reset anyway).
// Clear status register (read back first).
HAL_READ_UINT16(base+_REG_SCSSR, sr);
HAL_WRITE_UINT16(base+_REG_SCSSR, 0);
// Bring FIFO out of reset and set to trigger on every char in
// FIFO (or C-c input would not be processed).
HAL_WRITE_UINT8(base+_REG_SCFCR,
CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);
// Leave Tx/Rx interrupts disabled, but enable Tx/Rx
HAL_WRITE_UINT8(base+_REG_SCSCR,
CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
}
