static int hisfc350_reg_erase_one_block(struct hisfc_host *host,
struct hisfc_spi *spi,
unsigned int offset)
{
if (spi->driver->wait_ready(spi))
return 1;
spi->driver->write_enable(spi);
host->set_system_clock(host, spi->erase, TRUE);
hisfc_write(host, HISFC350_CMD_INS, spi->erase->cmd);
hisfc_write(host, HISFC350_CMD_ADDR,
(offset & HISFC350_CMD_ADDR_MASK));
hisfc_write(host, HISFC350_CMD_CONFIG,
HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
| HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->erase->iftype)
| HISFC350_CMD_CONFIG_DUMMY_CNT(spi->erase->dummy)
| HISFC350_CMD_CONFIG_ADDR_EN
| HISFC350_CMD_CONFIG_START);
HISFC350_CMD_WAIT_CPU_FINISH(host);
return 0;
}
/*
enable QE bit if QUAD read write is supported by SPI
*/
static int spi_mx25l25635e_qe_enable(struct hisfc_spi *spi)
{
struct hisfc_host *host = (struct hisfc_host *)spi->host;
unsigned int regval = 0;
unsigned int qe_op = 0;
if (hisfc350_is_quad(spi))
qe_op = MX_SPI_CMD_SR_QE;
else
qe_op = SPI_CMD_SR_XQE;
spi->driver->write_enable(spi);
hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_WRSR);
hisfc_write(host, HISFC350_CMD_DATABUF0, qe_op);
hisfc_write(host, HISFC350_CMD_CONFIG,
HISFC350_CMD_CONFIG_MEM_IF_TYPE(spi->
write->iftype)
| HISFC350_CMD_CONFIG_DATA_CNT(1)
| HISFC350_CMD_CONFIG_DATA_EN
| HISFC350_CMD_CONFIG_DUMMY_CNT(spi->
write->dummy)
| HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
| HISFC350_CMD_CONFIG_START);
HISFC350_CMD_WAIT_CPU_FINISH(host);
spi->driver->wait_ready(spi);
if (DEBUG_SPI) {
hisfc_write(host, HISFC350_CMD_INS, SPI_CMD_RDSR);
hisfc_write(host, HISFC350_CMD_CONFIG,
HISFC350_CMD_CONFIG_SEL_CS(spi->chipselect)
| HISFC350_CMD_CONFIG_DATA_CNT(1)
| HISFC350_CMD_CONFIG_DATA_EN
| HISFC350_CMD_CONFIG_RW_READ
| HISFC350_CMD_CONFIG_START);
HISFC350_CMD_WAIT_CPU_FINISH(host);
regval = hisfc_read(host, HISFC350_CMD_DATABUF0);
printf("QEbit = 0x40? : 0x%x\n", regval);
if ((regval & MX_SPI_CMD_SR_QE))
printf("QE bit enable success\n");
else
printf("QE bit enable failed\n");
}
return 0;
}
