BIT(FLOP),
BIT(NA),
BIT(LED),
BIT(ALGN),
BIT(RRST),
BIT(PARE),
BIT(TIMO),
ENDBITS
};
UNIT csr_unit = {
UDATA(NULL, UNIT_FIX, CSRSIZE)
};
REG csr_reg[] = {
{ HRDATADF(DATA, csr_data, 16, "CSR Data", csr_bits) },
{ NULL }
};
DEVICE csr_dev = {
"CSR", &csr_unit, csr_reg, NULL,
1, 16, 8, 4, 16, 32,
&csr_ex, &csr_dep, &csr_reset,
NULL, NULL, NULL, NULL,
DEV_DEBUG, 0, sys_deb_tab
};
t_stat csr_ex(t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
{
return SCPE_OK;
}
{ NULL }
};
DEVICE clk_dev = {
"TODR", &clk_unit, clk_reg, NULL,
1, 0, 8, 4, 0, 32,
NULL, NULL, &clk_reset,
NULL, &clk_attach, &clk_detach,
NULL, 0, 0, NULL, NULL, NULL, &clk_help, NULL, NULL,
&clk_description
};
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
REG tmr_reg[] = {
{ HRDATADF (ICCS, tmr_iccs, 32, "interval timer control and status", tmr_iccs_bits) },
{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
{ FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN },
{ NULL }
};
#define TMR_DB_REG 0x01 /* Register Access */
#define TMR_DB_TICK 0x02 /* Ticks */
#define TMR_DB_SCHED 0x04 /* Scheduling */
#define TMR_DB_INT 0x08 /* Interrupts */
DEBTAB tmr_deb[] = {
int32 wtc_csrc = 0;
int32 wtc_csrd = 0;
int32 wtc_mode = WTC_MODE_VMS;
t_stat wtc_set (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat wtc_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat wtc_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *wtc_description (DEVICE *dptr);
t_stat wtc_reset (DEVICE *dptr);
void wtc_set_valid (void);
void wtc_set_invalid (void);
UNIT wtc_unit = { UDATA (NULL, 0, 0) };
REG wtc_reg[] = {
{ HRDATADF (CSRA, wtc_csra, 8, "CSRA", wtc_csra_bits) },
{ HRDATADF (CSRB, wtc_csrb, 8, "CSRB", wtc_csrb_bits) },
{ HRDATADF (CSRC, wtc_csrc, 8, "CSRC", wtc_csrc_bits) },
{ HRDATADF (CSRD, wtc_csrd, 8, "CSRD", wtc_csrd_bits) },
{ HRDATADF (MODE, wtc_mode, 8, "Watch Mode", wtc_mode_bits) },
{ NULL }
};
MTAB wtc_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "TIME", "TIME={VMS|STD}", &wtc_set, &wtc_show, NULL, "Display watch time mode" },
{ 0 }
};
/* debugging bitmaps */
#define DBG_REG 0x0001 /* trace read/write registers */
