static sw_error_t
_horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t cmd)
{
sw_error_t rv;
a_uint32_t data;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (FAL_MAC_FRWRD == cmd) {
SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
} else if (FAL_MAC_DROP == cmd) {
SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
} else if (FAL_MAC_RDT_TO_CPU == cmd) {
SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
} else {
return SW_NOT_SUPPORTED;
}
HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_TRUE == enable)
{
data = 1;
}
else if (A_FALSE == enable)
{
data = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
sw_error_t
isis_leaky_init(a_uint32_t dev_id)
{
HSL_DEV_ID_CHECK(dev_id);
#ifndef HSL_STANDALONG
{
hsl_api_t *p_api;
SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
p_api->uc_leaky_mode_set = isis_uc_leaky_mode_set;
p_api->uc_leaky_mode_get = isis_uc_leaky_mode_get;
p_api->mc_leaky_mode_set = isis_mc_leaky_mode_set;
p_api->mc_leaky_mode_get = isis_mc_leaky_mode_get;
p_api->port_arp_leaky_set = isis_port_arp_leaky_set;
p_api->port_arp_leaky_get = isis_port_arp_leaky_get;
p_api->port_uc_leaky_set = isis_port_uc_leaky_set;
p_api->port_uc_leaky_get = isis_port_uc_leaky_get;
p_api->port_mc_leaky_set = isis_port_mc_leaky_set;
p_api->port_mc_leaky_get = isis_port_mc_leaky_get;
}
#endif
return SW_OK;
}
sw_error_t
shiva_fdb_init(a_uint32_t dev_id)
{
HSL_DEV_ID_CHECK(dev_id);
#ifndef HSL_STANDALONG
{
hsl_api_t *p_api;
SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
p_api->fdb_add = shiva_fdb_add;
p_api->fdb_del_all = shiva_fdb_del_all;
p_api->fdb_del_by_port = shiva_fdb_del_by_port;
p_api->fdb_del_by_mac = shiva_fdb_del_by_mac;
p_api->fdb_first = shiva_fdb_first;
p_api->fdb_find = shiva_fdb_find;
p_api->port_learn_set = shiva_fdb_port_learn_set;
p_api->port_learn_get = shiva_fdb_port_learn_get;
p_api->age_ctrl_set = shiva_fdb_age_ctrl_set;
p_api->age_ctrl_get = shiva_fdb_age_ctrl_get;
p_api->age_time_set = shiva_fdb_age_time_set;
p_api->age_time_get = shiva_fdb_age_time_get;
p_api->fdb_iterate = shiva_fdb_iterate;
}
#endif
return SW_OK;
}
static sw_error_t
_shiva_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
{
sw_error_t rv;
a_uint32_t reg = 0;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (FAL_FDB_DEL_STATIC & flag)
{
rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
}
else
{
rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
}
return rv;
}
static sw_error_t
_horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
fal_cable_status_t *cable_status, a_uint32_t *cable_len)
{
sw_error_t rv;
a_uint32_t phy_id = 0;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
if (NULL == phy_drv->phy_cdt)
return SW_NOT_SUPPORTED;
rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
SW_RTN_ON_ERROR(rv);
rv = phy_drv->phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
return rv;
}
static sw_error_t
_garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t * pport_egvlanmode)
{
sw_error_t rv;
a_uint32_t regval = 0;
fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
FAL_EG_TAGGED
};
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL(pport_egvlanmode);
HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
(a_uint8_t *) (®val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*pport_egvlanmode = retval[regval & 0x3];
return SW_OK;
}
static sw_error_t
_garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t mem_port_id)
{
sw_error_t rv;
a_uint32_t regval = 0;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (®val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
regval &= (~(0x1UL << mem_port_id));
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (®val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
{
sw_error_t rv;
a_uint32_t entry, data;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry);
if (data)
{
*enable = A_TRUE;
SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry);
*queue = data;
}
else
{
*enable = A_FALSE;
*queue = 0;
}
return SW_OK;
}
static sw_error_t
_shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (FAL_MAC_CPY_TO_CPU == cmd)
{
val = 1;
}
else if (FAL_MAC_RDT_TO_CPU == cmd)
{
val = 0;
}
else
{
return SW_NOT_SUPPORTED;
}
HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
{
sw_error_t rv;
a_uint32_t reg[3] = { 0, 0, 0 };
HSL_DEV_ID_CHECK(dev_id);
if ((A_TRUE == athena_fdb_is_zeroaddr(entry->addr))
&& (0 == entry->port.map)
&& (0 == entry->port.id))
{
return SW_BAD_PARAM;
}
rv = athena_atu_sw_to_hw(dev_id, entry, reg);
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
(a_uint8_t *) (®[2]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
rv = athena_fdb_commit(dev_id, ARL_LOAD_ENTRY);
return rv;
}
sw_error_t
garuda_portvlan_init(a_uint32_t dev_id)
{
HSL_DEV_ID_CHECK(dev_id);
#ifndef HSL_STANDALONG
hsl_api_t *p_api;
SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
p_api->port_1qmode_get = garuda_port_1qmode_get;
p_api->port_1qmode_set = garuda_port_1qmode_set;
p_api->port_egvlanmode_get = garuda_port_egvlanmode_get;
p_api->port_egvlanmode_set = garuda_port_egvlanmode_set;
p_api->portvlan_member_add = garuda_portvlan_member_add;
p_api->portvlan_member_del = garuda_portvlan_member_del;
p_api->portvlan_member_update = garuda_portvlan_member_update;
p_api->portvlan_member_get = garuda_portvlan_member_get;
p_api->port_default_vid_set = garuda_port_default_vid_set;
p_api->port_default_vid_get = garuda_port_default_vid_get;
p_api->port_force_default_vid_set = garuda_port_force_default_vid_set;
p_api->port_force_default_vid_get = garuda_port_force_default_vid_get;
p_api->port_force_portvlan_set = garuda_port_force_portvlan_set;
p_api->port_force_portvlan_get = garuda_port_force_portvlan_get;
p_api->port_nestvlan_set = garuda_port_nestvlan_set;
p_api->port_nestvlan_get = garuda_port_nestvlan_get;
p_api->nestvlan_tpid_set = garuda_nestvlan_tpid_set;
p_api->nestvlan_tpid_get = garuda_nestvlan_tpid_get;
#endif
return SW_OK;
}
static sw_error_t
_garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
fal_pbmp_t mem_port_map)
{
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_FALSE ==
hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * status)
{
a_uint32_t phy_id;
sw_error_t rv;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
if (NULL == phy_drv->phy_autoneg_status_get)
return SW_NOT_SUPPORTED;
rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
SW_RTN_ON_ERROR(rv);
*status = phy_drv->phy_autoneg_status_get(dev_id, phy_id);
return SW_OK;
}
static sw_error_t
_garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if ((0 == vid) || (vid > MAX_VLAN_ID))
{
return SW_BAD_PARAM;
}
val = vid;
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return rv;
}
static sw_error_t
_garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t port_1qmode)
{
sw_error_t rv;
a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (FAL_1Q_MODE_BUTT <= port_1qmode)
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
(a_uint8_t *) (®val[port_1qmode]),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_duplex_t * pduplex)
{
sw_error_t rv;
a_uint32_t phy_id;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
if (NULL == phy_drv->phy_duplex_get)
return SW_NOT_SUPPORTED;
rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
SW_RTN_ON_ERROR(rv);
rv = phy_drv->phy_duplex_get(dev_id, phy_id, pduplex);
return rv;
}
static sw_error_t
_garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
FORCE_PVLAN, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
{
sw_error_t rv;
a_uint32_t reg[3] = { 0, 0, 0 };
HSL_DEV_ID_CHECK(dev_id);
rv = shiva_atu_sw_to_hw(dev_id, entry, reg);
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
(a_uint8_t *) (®[2]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
rv = shiva_fdb_commit(dev_id, ARL_LOAD_ENTRY);
return rv;
}
static sw_error_t
_garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
FORCE_PVLAN, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable)
{
data = 1;
}
else if (A_FALSE == enable)
{
data = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t * pport_1qmode)
{
sw_error_t rv;
a_uint32_t regval = 0;
fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
FAL_1Q_CHECK, FAL_1Q_SECURE
};
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL(pport_1qmode);
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
(a_uint8_t *) (®val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*pport_1qmode = retval[regval & 0x3];
return SW_OK;
}
static sw_error_t
_isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t *enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == data)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t port_egvlanmode)
{
sw_error_t rv;
a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3 };
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (FAL_EG_MODE_BUTT <= port_egvlanmode)
{
return SW_BAD_PARAM;
}
if (FAL_EG_HYBRID == port_egvlanmode)
{
return SW_NOT_SUPPORTED;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
(a_uint8_t *) (®val[port_egvlanmode]),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_isis_mc_leaky_mode_set(a_uint32_t dev_id,
fal_leaky_ctrl_mode_t ctrl_mode)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
{
data = 0;
}
else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
{
data = 1;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t reg, field;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
field = reg & (0x1 << port_id);
if (field) {
*enable = A_FALSE;
} else {
*enable = A_TRUE;
}
return SW_OK;
}
