/***********************************************************************
*
* Function: i2s_default
*
* Purpose: Places the ISC interface and controller in a default state
*
* Processing:
* See Function
* Parameters:
* i2sregs: Pointer to an I2S register set
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
**********************************************************************/
STATIC void i2s_default(I2S_REGS_T *i2sregs)
{
/* Setup default state of I2S in DEFAULT mode, with all
channels set up in a safe configuration, and all
interrupts masked. 16Bit Stereo, 48KHz (assuming 104MHz HCLK)
FIFO Interrupt depth set to 8 (not DMA) */
/* Set transmit channel to default state, master mode, 16bit */
i2sregs->i2s_dao = I2S_STOP | I2S_WW16 | I2S_WS_HP(I2S_WW16_HP);
/* Set receive channel to default state, slave mode, 16bit */
i2sregs->i2s_dai = I2S_STOP | I2S_WW16 | I2S_WS_SEL
| I2S_WS_HP(I2S_WW16_HP);
/* reset Tx rate to default */
i2sregs->i2s_tx_rate = A48KHZ104MHZ16BIT;
/* reset Rx rate to default */
i2sregs->i2s_rx_rate = A48KHZ104MHZ16BIT;
/* clear the DMA configuration register */
i2sregs->i2s_dma0 = i2sregs->i2s_dma1 = 0;
/* Set the Tx/Rx FIFO Trigger levels */
i2sregs->i2s_irq = (I2S_IRQ_TX_DEPTH(8) | I2S_IRQ_RX_DEPTH(8));
}
/* Enable/Disable Interrupt with a specific FIFO depth */
void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth)
{
uint32_t temp;
depth &= 0x0F;
if (newState == ENABLE) {
pI2S->IRQ |= 0x02;
}
else {
pI2S->IRQ &= (~0x02);
}
temp = pI2S->IRQ & (~I2S_IRQ_TX_DEPTH_MASK);
pI2S->IRQ = temp | (I2S_IRQ_TX_DEPTH(depth));
}
