/*
** ===================================================================
** Method : I2S0_Init (component Init_I2S)
** Description :
** This method initializes registers of the I2S module
** according to the Peripheral Initialization settings.
** Call this method in user code to initialize the module. By
** default, the method is called by PE automatically; see "Call
** Init method" property of the component for more details.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
void I2S0_Init(void)
{
/* SIM_SCGC6: I2S=1 */
SIM_SCGC6 |= SIM_SCGC6_I2S_MASK;
/* I2S0_MCR: DUF=0,MOE=0,??=0,??=0,??=0,??=0,MICS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
I2S0_MCR = I2S_MCR_MICS(0x00);
while ((I2S0_MCR & I2S_MCR_MOE_MASK) != 0U) {} /* Wait for MCLK disable */
/* I2S0_MCR: DUF=0,MOE=0,??=0,??=0,??=0,??=0,MICS=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
I2S0_MCR = I2S_MCR_MICS(0x01);
/* I2S0_MDR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FRACT=0,DIVIDE=0 */
I2S0_MDR = (I2S_MDR_FRACT(0x00) | I2S_MDR_DIVIDE(0x00));
/* I2S0_MCR: MOE=1 */
I2S0_MCR |= I2S_MCR_MOE_MASK;
/* I2S0_TCSR: TE=0,STOPE=0,DBGE=0,BCE=0,??=0,??=0,FR=1,SR=0,??=0,??=0,??=0,WSF=1,SEF=1,FEF=1,FWF=1,??=1,??=1,??=1,??=1,WSIE=0,SEIE=0,FEIE=0,FWIE=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FWDE=0,??=0 */
I2S0_TCSR = I2S_TCSR_FR_MASK |
I2S_TCSR_WSF_MASK |
I2S_TCSR_SEF_MASK |
I2S_TCSR_FEF_MASK |
I2S_TCSR_FWF_MASK |
0x0001E000U;
while ((I2S0_TCSR & I2S_TCSR_TE_MASK) != 0U) {} /* Wait for transmitter disable */
/* I2S0_RCSR: RE=0,STOPE=0,DBGE=0,BCE=0,??=0,??=0,FR=1,SR=0,??=0,??=0,??=0,WSF=1,SEF=1,FEF=1,FWF=0,??=0,??=0,??=0,??=0,WSIE=0,SEIE=0,FEIE=0,FWIE=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FWDE=0,??=0 */
I2S0_RCSR = I2S_RCSR_FR_MASK |
I2S_RCSR_WSF_MASK |
I2S_RCSR_SEF_MASK |
I2S_RCSR_FEF_MASK;
while ((I2S0_RCSR & I2S_RCSR_RE_MASK) != 0U) {} /* Wait for receiver disable */
/* I2S0_TCR2: SYNC=0,BCS=0,BCI=0,MSEL=0,BCP=0,BCD=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DIV=1 */
I2S0_TCR2 = I2S_TCR2_SYNC(0x00) |
I2S_TCR2_MSEL(0x00) |
I2S_TCR2_BCD_MASK |
I2S_TCR2_DIV(0x01);
/* I2S0_RCR2: SYNC=0,BCS=0,BCI=0,MSEL=0,BCP=0,BCD=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DIV=1 */
I2S0_RCR2 = I2S_RCR2_SYNC(0x00) |
I2S_RCR2_MSEL(0x00) |
I2S_RCR2_BCD_MASK |
I2S_RCR2_DIV(0x01);
/* I2S0_TCR3: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TCE=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,WDFL=0 */
I2S0_TCR3 = 0x00U;
/* I2S0_RCR3: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RCE=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,WDFL=0 */
I2S0_RCR3 = 0x00U;
/* I2S0_TCR4: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FRSZ=0,??=0,??=0,??=0,SYWD=0,??=0,??=0,??=0,MF=0,FSE=0,??=0,FSP=0,FSD=1 */
I2S0_TCR4 = (I2S_TCR4_SYWD(0x00) | I2S_TCR4_FSD_MASK);
/* I2S0_RCR4: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FRSZ=0,??=0,??=0,??=0,SYWD=0,??=0,??=0,??=0,MF=0,FSE=0,??=0,FSP=0,FSD=1 */
I2S0_RCR4 = (I2S_RCR4_SYWD(0x00) | I2S_RCR4_FSD_MASK);
/* I2S0_TCR5: ??=0,??=0,??=0,WNW=7,??=0,??=0,??=0,W0W=7,??=0,??=0,??=0,FBT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
I2S0_TCR5 = (I2S_TCR5_WNW(0x07) | I2S_TCR5_W0W(0x07) | I2S_TCR5_FBT(0x00));
/* I2S0_RCR5: ??=0,??=0,??=0,WNW=7,??=0,??=0,??=0,W0W=7,??=0,??=0,??=0,FBT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
I2S0_RCR5 = (I2S_RCR5_WNW(0x07) | I2S_RCR5_W0W(0x07) | I2S_RCR5_FBT(0x00));
/* I2S0_TMR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TWM=0 */
I2S0_TMR = I2S_TMR_TWM(0x00);
/* I2S0_RMR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RWM=0 */
I2S0_RMR = I2S_RMR_RWM(0x00);
/* I2S0_TCSR: TE=0,STOPE=0,DBGE=0,BCE=0,??=0,??=0,FR=0,SR=0,??=0,??=0,??=0,WSF=0,SEF=0,FEF=0,FWF=0,??=0,??=0,??=0,??=0,WSIE=0,SEIE=0,FEIE=0,FWIE=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FWDE=0,??=0 */
I2S0_TCSR = 0x00U;
/* I2S0_RCSR: RE=0,STOPE=0,DBGE=0,BCE=0,??=0,??=0,FR=0,SR=0,??=0,??=0,??=0,WSF=0,SEF=0,FEF=0,FWF=0,??=0,??=0,??=0,??=0,WSIE=0,SEIE=0,FEIE=0,FWIE=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FWDE=0,??=0 */
I2S0_RCSR = 0x00U;
}
void AudioOutputI2S2::config_i2s(void)
{
CCM_CCGR5 |= CCM_CCGR5_SAI2(CCM_CCGR_ON);
//PLL:
int fs = AUDIO_SAMPLE_RATE_EXACT;
// PLL between 27*24 = 648MHz und 54*24=1296MHz
int n1 = 4; //SAI prescaler 4 => (n1*n2) = multiple of 4
int n2 = 1 + (24000000 * 27) / (fs * 256 * n1);
double C = ((double)fs * 256 * n1 * n2) / 24000000;
int c0 = C;
int c2 = 10000;
int c1 = C * c2 - (c0 * c2);
set_audioClock(c0, c1, c2);
// clear SAI2_CLK register locations
CCM_CSCMR1 = (CCM_CSCMR1 & ~(CCM_CSCMR1_SAI2_CLK_SEL_MASK))
| CCM_CSCMR1_SAI2_CLK_SEL(2); // &0x03 // (0,1,2): PLL3PFD0, PLL5, PLL4,
CCM_CS2CDR = (CCM_CS2CDR & ~(CCM_CS2CDR_SAI2_CLK_PRED_MASK | CCM_CS2CDR_SAI2_CLK_PODF_MASK))
| CCM_CS2CDR_SAI2_CLK_PRED(n1-1)
| CCM_CS2CDR_SAI2_CLK_PODF(n2-1);
IOMUXC_GPR_GPR1 = (IOMUXC_GPR_GPR1 & ~(IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK))
| (IOMUXC_GPR_GPR1_SAI2_MCLK_DIR | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(0)); //Select MCLK
// if either transmitter or receiver is enabled, do nothing
if (I2S2_TCSR & I2S_TCSR_TE) return;
if (I2S2_RCSR & I2S_RCSR_RE) return;
CORE_PIN5_CONFIG = 2; //2:MCLK
CORE_PIN4_CONFIG = 2; //2:TX_BCLK
CORE_PIN3_CONFIG = 2; //2:TX_SYNC
// CORE_PIN2_CONFIG = 2; //2:TX_DATA0
// CORE_PIN33_CONFIG = 2; //2:RX_DATA0
int rsync = 1;
int tsync = 0;
I2S2_TMR = 0;
//I2S2_TCSR = (1<<25); //Reset
I2S2_TCR1 = I2S_TCR1_RFW(1);
I2S2_TCR2 = I2S_TCR2_SYNC(tsync) | I2S_TCR2_BCP // sync=0; tx is async;
| (I2S_TCR2_BCD | I2S_TCR2_DIV((1)) | I2S_TCR2_MSEL(1));
I2S2_TCR3 = I2S_TCR3_TCE;
I2S2_TCR4 = I2S_TCR4_FRSZ((2-1)) | I2S_TCR4_SYWD((32-1)) | I2S_TCR4_MF | I2S_TCR4_FSD | I2S_TCR4_FSE | I2S_TCR4_FSP;
I2S2_TCR5 = I2S_TCR5_WNW((32-1)) | I2S_TCR5_W0W((32-1)) | I2S_TCR5_FBT((32-1));
I2S2_RMR = 0;
//I2S2_RCSR = (1<<25); //Reset
I2S2_RCR1 = I2S_RCR1_RFW(1);
I2S2_RCR2 = I2S_RCR2_SYNC(rsync) | I2S_RCR2_BCP // sync=0; rx is async;
| (I2S_RCR2_BCD | I2S_RCR2_DIV((1)) | I2S_RCR2_MSEL(1));
I2S2_RCR3 = I2S_RCR3_RCE;
I2S2_RCR4 = I2S_RCR4_FRSZ((2-1)) | I2S_RCR4_SYWD((32-1)) | I2S_RCR4_MF | I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
I2S2_RCR5 = I2S_RCR5_WNW((32-1)) | I2S_RCR5_W0W((32-1)) | I2S_RCR5_FBT((32-1));
}
void AudioOutputI2S::config_i2s(void)
{
SIM_SCGC6 |= SIM_SCGC6_I2S;
SIM_SCGC7 |= SIM_SCGC7_DMA;
SIM_SCGC6 |= SIM_SCGC6_DMAMUX;
// if either transmitter or receiver is enabled, do nothing
if (I2S0_TCSR & I2S_TCSR_TE) return;
if (I2S0_RCSR & I2S_RCSR_RE) return;
// enable MCLK output
I2S0_MCR = I2S_MCR_MICS(MCLK_SRC) | I2S_MCR_MOE;
while (I2S0_MCR & I2S_MCR_DUF) ;
I2S0_MDR = I2S_MDR_FRACT((MCLK_MULT-1)) | I2S_MDR_DIVIDE((MCLK_DIV-1));
// configure transmitter
I2S0_TMR = 0;
I2S0_TCR1 = I2S_TCR1_TFW(1); // watermark at half fifo size
I2S0_TCR2 = I2S_TCR2_SYNC(0) | I2S_TCR2_BCP | I2S_TCR2_MSEL(1)
| I2S_TCR2_BCD | I2S_TCR2_DIV(1);
I2S0_TCR3 = I2S_TCR3_TCE;
I2S0_TCR4 = I2S_TCR4_FRSZ(1) | I2S_TCR4_SYWD(31) | I2S_TCR4_MF
| I2S_TCR4_FSE | I2S_TCR4_FSP | I2S_TCR4_FSD;
I2S0_TCR5 = I2S_TCR5_WNW(31) | I2S_TCR5_W0W(31) | I2S_TCR5_FBT(31);
// configure receiver (sync'd to transmitter clocks)
I2S0_RMR = 0;
I2S0_RCR1 = I2S_RCR1_RFW(1);
I2S0_RCR2 = I2S_RCR2_SYNC(1) | I2S_TCR2_BCP | I2S_RCR2_MSEL(1)
| I2S_RCR2_BCD | I2S_RCR2_DIV(1);
I2S0_RCR3 = I2S_RCR3_RCE;
I2S0_RCR4 = I2S_RCR4_FRSZ(1) | I2S_RCR4_SYWD(31) | I2S_RCR4_MF
| I2S_RCR4_FSE | I2S_RCR4_FSP | I2S_RCR4_FSD;
I2S0_RCR5 = I2S_RCR5_WNW(31) | I2S_RCR5_W0W(31) | I2S_RCR5_FBT(31);
// configure pin mux for 3 clock signals
CORE_PIN23_CONFIG = PORT_PCR_MUX(6); // pin 23, PTC2, I2S0_TX_FS (LRCLK)
CORE_PIN9_CONFIG = PORT_PCR_MUX(6); // pin 9, PTC3, I2S0_TX_BCLK
CORE_PIN11_CONFIG = PORT_PCR_MUX(6); // pin 11, PTC6, I2S0_MCLK
}