/**
* Executes one (or perhaps a few more) IO instruction(s).
*
* @returns VBox status code suitable for EM.
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure.
*/
static int emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
{
PCPUMCTX pCtx = pVCpu->em.s.pCtx;
STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
/*
* Try to restart the io instruction that was refused in ring-0.
*/
VBOXSTRICTRC rcStrict = HMR3RestartPendingIOInstr(pVM, pVCpu, pCtx);
if (IOM_SUCCESS(rcStrict))
{
STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
return VBOXSTRICTRC_TODO(rcStrict); /* rip already updated. */
}
AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
RT_SUCCESS_NP(rcStrict) ? VERR_IPE_UNEXPECTED_INFO_STATUS : VBOXSTRICTRC_TODO(rcStrict));
/*
* Hand it over to the interpreter.
*/
rcStrict = IEMExecOne(pVCpu);
LogFlow(("emR3HmExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
return VBOXSTRICTRC_TODO(rcStrict);
}
/**
* Executes one (or perhaps a few more) IO instruction(s).
*
* @returns VBox status code suitable for EM.
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure.
*/
static int emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
{
RT_NOREF(pVM);
STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
VBOXSTRICTRC rcStrict;
uint32_t idxContinueExitRec = pVCpu->em.s.idxContinueExitRec;
RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
if (idxContinueExitRec >= RT_ELEMENTS(pVCpu->em.s.aExitRecords))
{
/*
* Hand it over to the interpreter.
*/
CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
rcStrict = IEMExecOne(pVCpu);
LogFlow(("emR3HmExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
}
else
{
RT_UNTRUSTED_VALIDATED_FENCE();
CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
rcStrict = EMHistoryExec(pVCpu, &pVCpu->em.s.aExitRecords[idxContinueExitRec], 0);
LogFlow(("emR3HmExecuteIOInstruction: %Rrc (EMHistoryExec)\n", VBOXSTRICTRC_VAL(rcStrict)));
STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
}
STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
return VBOXSTRICTRC_TODO(rcStrict);
}
static int emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
#endif
{
NOREF(rcRC);
#ifdef LOG_ENABLED
/*
* Log it.
*/
Log(("EMINS: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
if (pszPrefix)
{
DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", pszPrefix);
DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
}
#endif
/*
* Use IEM and fallback on REM if the functionality is missing.
* Once IEM gets mature enough, nothing should ever fall back.
*/
STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
VBOXSTRICTRC rcStrict;
uint32_t idxContinueExitRec = pVCpu->em.s.idxContinueExitRec;
RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
if (idxContinueExitRec >= RT_ELEMENTS(pVCpu->em.s.aExitRecords))
{
CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
rcStrict = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
}
else
{
RT_UNTRUSTED_VALIDATED_FENCE();
rcStrict = EMHistoryExec(pVCpu, &pVCpu->em.s.aExitRecords[idxContinueExitRec], 0);
LogFlow(("emR3HmExecuteInstruction: %Rrc (EMHistoryExec)\n", VBOXSTRICTRC_VAL(rcStrict)));
}
STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
if ( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
|| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
{
#ifdef VBOX_WITH_REM
STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
EMRemLock(pVM);
/* Flush the recompiler TLB if the VCPU has changed. */
if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
pVM->em.s.idLastRemCpu = pVCpu->idCpu;
rcStrict = REMR3EmulateInstruction(pVM, pVCpu);
EMRemUnlock(pVM);
STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
#else /* !VBOX_WITH_REM */
NOREF(pVM);
#endif /* !VBOX_WITH_REM */
}
return VBOXSTRICTRC_TODO(rcStrict);
}
static int emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
#endif
{
#ifdef LOG_ENABLED
PCPUMCTX pCtx = pVCpu->em.s.pCtx;
#endif
int rc;
NOREF(rcRC);
#ifdef LOG_ENABLED
/*
* Log it.
*/
Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
if (pszPrefix)
{
DBGFR3_INFO_LOG(pVM, "cpumguest", pszPrefix);
DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
}
#endif
/*
* Use IEM and fallback on REM if the functionality is missing.
* Once IEM gets mature enough, nothing should ever fall back.
*/
STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
|| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
{
#ifdef VBOX_WITH_REM
STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
EMRemLock(pVM);
/* Flush the recompiler TLB if the VCPU has changed. */
if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
pVM->em.s.idLastRemCpu = pVCpu->idCpu;
rc = REMR3EmulateInstruction(pVM, pVCpu);
EMRemUnlock(pVM);
STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
#else /* !VBOX_WITH_REM */
NOREF(pVM);
#endif /* !VBOX_WITH_REM */
}
#ifdef EM_NOTIFY_HM
if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HM)
HMR3NotifyEmulated(pVCpu);
#endif
return rc;
}
static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
#endif
{
#ifdef LOG_ENABLED
PCPUMCTX pCtx = pVCpu->em.s.pCtx;
#endif
int rc;
NOREF(rcRC);
/*
*
* The simple solution is to use the recompiler.
* The better solution is to disassemble the current instruction and
* try handle as many as possible without using REM.
*
*/
#ifdef LOG_ENABLED
/*
* Disassemble the instruction if requested.
*/
if (pszPrefix)
{
DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
}
#endif /* LOG_ENABLED */
#if 0
/* Try our own instruction emulator before falling back to the recompiler. */
DISCPUSTATE Cpu;
rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
if (RT_SUCCESS(rc))
{
switch (Cpu.pCurInstr->uOpcode)
{
/* @todo we can do more now */
case OP_MOV:
case OP_AND:
case OP_OR:
case OP_XOR:
case OP_POP:
case OP_INC:
case OP_DEC:
case OP_XCHG:
STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
rc = EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0);
if (RT_SUCCESS(rc))
{
#ifdef EM_NOTIFY_HWACCM
if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
HWACCMR3NotifyEmulated(pVCpu);
#endif
STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
return rc;
}
if (rc != VERR_EM_INTERPRETER)
AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
break;
}
}
#endif /* 0 */
STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
#ifdef VBOX_WITH_REM
EMRemLock(pVM);
/* Flush the recompiler TLB if the VCPU has changed. */
if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
pVM->em.s.idLastRemCpu = pVCpu->idCpu;
rc = REMR3EmulateInstruction(pVM, pVCpu);
EMRemUnlock(pVM);
#else
rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
#endif
STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
#ifdef EM_NOTIFY_HWACCM
if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
HWACCMR3NotifyEmulated(pVCpu);
#endif
return rc;
}
/**
* Common worker for the \#PF handler and IOMMMIOPhysHandler (APIC+VT-x).
*
* @returns VBox status code (appropriate for GC return).
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure of the calling EMT.
* @param uErrorCode CPU Error code. This is UINT32_MAX when we don't have
* any error code (the EPT misconfig hack).
* @param pCtxCore Trap register frame.
* @param GCPhysFault The GC physical address corresponding to pvFault.
* @param pvUser Pointer to the MMIO ring-3 range entry.
*/
static VBOXSTRICTRC iomMmioCommonPfHandler(PVM pVM, PVMCPU pVCpu, uint32_t uErrorCode, PCPUMCTXCORE pCtxCore,
RTGCPHYS GCPhysFault, void *pvUser)
{
int rc = IOM_LOCK_SHARED(pVM);
#ifndef IN_RING3
if (rc == VERR_SEM_BUSY)
return VINF_IOM_R3_MMIO_READ_WRITE;
#endif
AssertRC(rc);
STAM_PROFILE_START(&pVM->iom.s.StatRZMMIOHandler, a);
Log(("iomMmioCommonPfHandler: GCPhys=%RGp uErr=%#x rip=%RGv\n", GCPhysFault, uErrorCode, (RTGCPTR)pCtxCore->rip));
PIOMMMIORANGE pRange = (PIOMMMIORANGE)pvUser;
Assert(pRange);
Assert(pRange == iomMmioGetRange(pVM, pVCpu, GCPhysFault));
iomMmioRetainRange(pRange);
#ifndef VBOX_WITH_STATISTICS
IOM_UNLOCK_SHARED(pVM);
#else
/*
* Locate the statistics.
*/
PIOMMMIOSTATS pStats = iomMmioGetStats(pVM, pVCpu, GCPhysFault, pRange);
if (!pStats)
{
iomMmioReleaseRange(pVM, pRange);
# ifdef IN_RING3
return VERR_NO_MEMORY;
# else
STAM_PROFILE_STOP(&pVM->iom.s.StatRZMMIOHandler, a);
STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIOFailures);
return VINF_IOM_R3_MMIO_READ_WRITE;
# endif
}
#endif
#ifndef IN_RING3
/*
* Should we defer the request right away? This isn't usually the case, so
* do the simple test first and the try deal with uErrorCode being N/A.
*/
if (RT_UNLIKELY( ( !pRange->CTX_SUFF(pfnWriteCallback)
|| !pRange->CTX_SUFF(pfnReadCallback))
&& ( uErrorCode == UINT32_MAX
? pRange->pfnWriteCallbackR3 || pRange->pfnReadCallbackR3
: uErrorCode & X86_TRAP_PF_RW
? !pRange->CTX_SUFF(pfnWriteCallback) && pRange->pfnWriteCallbackR3
: !pRange->CTX_SUFF(pfnReadCallback) && pRange->pfnReadCallbackR3
)
)
)
{
if (uErrorCode & X86_TRAP_PF_RW)
STAM_COUNTER_INC(&pStats->CTX_MID_Z(Write,ToR3));
else
STAM_COUNTER_INC(&pStats->CTX_MID_Z(Read,ToR3));
STAM_PROFILE_STOP(&pVM->iom.s.StatRZMMIOHandler, a);
STAM_COUNTER_INC(&pVM->iom.s.StatRZMMIOFailures);
iomMmioReleaseRange(pVM, pRange);
return VINF_IOM_R3_MMIO_READ_WRITE;
}
#endif /* !IN_RING3 */
/*
* Retain the range and do locking.
*/
PPDMDEVINS pDevIns = pRange->CTX_SUFF(pDevIns);
rc = PDMCritSectEnter(pDevIns->CTX_SUFF(pCritSectRo), VINF_IOM_R3_MMIO_READ_WRITE);
if (rc != VINF_SUCCESS)
{
iomMmioReleaseRange(pVM, pRange);
return rc;
}
/*
* Let IEM call us back via iomMmioHandler.
*/
VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
NOREF(pCtxCore); NOREF(GCPhysFault);
STAM_PROFILE_STOP(&pVM->iom.s.StatRZMMIOHandler, a);
PDMCritSectLeave(pDevIns->CTX_SUFF(pCritSectRo));
iomMmioReleaseRange(pVM, pRange);
if (RT_SUCCESS(rcStrict))
return rcStrict;
if ( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
|| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
{
Log(("IOM: Hit unsupported IEM feature!\n"));
rcStrict = VINF_EM_RAW_EMULATE_INSTR;
}
return rcStrict;
}
