int
bcm_timer_delete(bcm_timer_id timer_id)
{
ecos_timer_entry_t *entry = (ecos_timer_entry_t *)timer_id;
ecos_timer_list_t *list = entry->list;
int status;
int key;
TIMERDBG("entry %08x timer %08x", entry, entry->timer);
/* make sure no interrupts can happen */
key = INTLOCK();
/* lock the timer list */
TIMER_LIST_LOCK(list);
/* remove the entry from the used list first */
status = remove_entry(&list->used, entry);
if (status != 0)
goto exit0;
/* delete the backend timer */
ecos_del_timer(entry);
/* free the entry back to freed list */
put_entry(&list->freed, entry);
entry->flags = TIMER_FLAG_NONE;
entry->list = NULL;
TIMER_LIST_UNLOCK(list);
INTUNLOCK(key);
TIMERDBG("done");
return 0;
/* error handling */
exit0:
TIMER_LIST_UNLOCK(list);
INTUNLOCK(key);
return status;
}
/*
* Cleanup internal resources used by this timer module. It deletes all
* pending timer entries from the backend timer system as well.
*/
int
bcm_timer_module_cleanup(bcm_timer_module_id module_id)
{
ecos_timer_list_t *list = (ecos_timer_list_t *)module_id;
ecos_timer_entry_t *entry;
int key;
TIMERDBG("list %08x", list);
/*
* do nothing if the list has not been initialized
*/
if (!(list->flags&TIMER_LIST_FLAG_INIT))
return -1;
/*
* mark the big bang flag here so that no more callbacks
* shall be scheduled or called from this point on...
*/
list->flags |= TIMER_LIST_FLAG_EXIT;
/*
* remove all backend timers here so that no timer expires after here.
*/
TIMER_LIST_LOCK(list);
key = INTLOCK();
for (entry = list->used; entry != NULL; entry = entry->next)
{
ecos_del_timer(entry);
}
INTUNLOCK(key);
TIMER_LIST_UNLOCK(list);
/*
* have to wait till all expired entries to have been handled
*/
for (entry = list->used; entry != NULL; entry = entry->next)
{
if ((entry->flags&TIMER_FLAG_DEFERRED) &&
!(entry->flags&TIMER_FLAG_FINISHED))
break;
}
cyg_mutex_destroy(&(list->lock));
/* now it should be safe to blindly free all the resources */
TIMER_FREE_LOCK_MECHANISM();
free(list);
TIMERDBG("done");
return 0;
}
BOOL AddDMABufferList ( UINT32 uDMACh,UINT32* pSBuff,UINT32 uBuffSize)
{
UINT32 OldLevel;
register BOOL bReturn;
/* Note : uBuffSize from BM must be <= 64 */
if ( (pSBuff == 0) || (uBuffSize > BULK_MAX_PACKET_SIZE) )
return FALSE;
/* Initialize variables to error and no BM operation (pEPBM = 0) */
bReturn = FALSE;
OldLevel = INTLOCK();
switch ( uDMACh )
{
#if DSL_DMA
case DMA_CHANNEL_DSL_TX : /* 5 */
bReturn = DSLWriteBuffer(pSBuff,uBuffSize);
if (bReturn == 0)
{
DSLInfo.TxRejectCnt += 1;
}
break;
#endif
case DMA_CHANNEL_USB_TX_EP1 : /* 11 */
case DMA_CHANNEL_USB_TX_EP2 : /* 10 */
case DMA_CHANNEL_USB_TX_EP3 : /* 9 */
case DMA_CHANNEL_USB_TX_EP0 : /* 13 */
case DMA_CHANNEL_EMAC1_TX :
case DMA_CHANNEL_EMAC2_TX :
default :
break;
}
INTUNLOCK(OldLevel);
return bReturn;
}
/*
** The actual handware interrupt goes here for processing.
*/
void GPIOHandler(int irq, void *dev_id, struct pt_regs * regs)
{
register UINT32 i;
register UINT32 dwGPIO1Stat, dwGPIO2Stat, dwGPIO3Stat;
register UINT32 BitPosition;
register int oldlevel;
#ifdef INSTRUMENTATION
register int oldTskGPIO;
#endif /* INSTRUMENTATION */
oldlevel = INTLOCK();
#ifdef INSTRUMENTATION
oldTskGPIO= ReadGPIOData(GPOUT_TASKRDY_LED);
WriteGPIOData(GPOUT_TASKRDY_LED, LED_ON);
#endif /* INSTRUMENTATION */
while (1)
{
/* Each GPIO ISR only contains 16 bits */
dwGPIO1Stat = (*p_GRP0_INT_STAT & *p_GRP0_INT_MASK) & 0xFFFF;
dwGPIO2Stat = (*p_GRP1_INT_STAT & *p_GRP1_INT_MASK) & 0xFFFF;
dwGPIO3Stat = (*p_GRP2_INT_STAT & *p_GRP2_INT_MASK) & 0xFFFF;
if ( (dwGPIO1Stat | dwGPIO2Stat | dwGPIO3Stat) == 0)
break;
for (i = 0, BitPosition = 1; dwGPIO1Stat; i++, BitPosition<<=1)
if (dwGPIO1Stat & BitPosition)
{
if (GPIOISR1Handler_Tbl[i] != 0)
(*GPIOISR1Handler_Tbl[i])(i);
else
{
if (pGPIO_ISR[i] != 0)
(*(pGPIO_ISR)[i])(i);
HW_REG_WRITE (p_GRP0_INT_STAT, BitPosition);
}
dwGPIO1Stat &= ~(BitPosition);
}
for (i = 0, BitPosition = 1; dwGPIO2Stat; i++, BitPosition<<=1)
if (dwGPIO2Stat & BitPosition)
{
if (GPIOISR2Handler_Tbl[i] != 0)
(*GPIOISR2Handler_Tbl[i])(i+16);
else
{
if (pGPIO_ISR[i+16] != 0)
(*(pGPIO_ISR)[i+16])(i+16);
HW_REG_WRITE (p_GRP1_INT_STAT, BitPosition);
}
dwGPIO2Stat &= ~(BitPosition);
}
for (i = 0, BitPosition = 1; dwGPIO3Stat; i++, BitPosition<<=1)
if (dwGPIO3Stat & BitPosition)
{
if (GPIOISR3Handler_Tbl[i] != 0)
(*GPIOISR3Handler_Tbl[i])(i+32);
else
{
if (pGPIO_ISR[i+32] != 0)
(*(pGPIO_ISR)[i+32])(i+32);
HW_REG_WRITE (p_GRP2_INT_STAT, BitPosition);
}
dwGPIO3Stat &= ~(BitPosition);
}
}
#ifdef INSTRUMENTATION
WriteGPIOData(GPOUT_TASKRDY_LED, oldTskGPIO);
#endif /* INSTRUMENTATION */
HW_REG_WRITE (PIC_TOP_ISR_IRQ, INT_GPIO);
INTUNLOCK(oldlevel);
}
BOOL DMAFlushChannelBuff(UINT32 uDMACh)
{
UINT32 OldLevel = 0;
register BOOL bReturn = FALSE;
/* Need to turn off interrupts here since background task is modifying a */
/* variable that is accessible also from interrupt context. */
OldLevel = INTLOCK();
switch ( uDMACh )
{
case DMA_CHANNEL_USB_TX_EP0 : /* 13 */
case DMA_CHANNEL_USB_TX_EP1 : /* 11 */
case DMA_CHANNEL_USB_TX_EP3 : /* 9 */
case DMA_CHANNEL_USB_TX_EP2 : /* 10 */
case DMA_CHANNEL_USB_RX_EP0 :
case DMA_CHANNEL_USB_RX_EP1 :
case DMA_CHANNEL_USB_RX_EP2 :
case DMA_CHANNEL_USB_RX_EP3 :
break;
case DMA_CHANNEL_M2M_IN :
case DMA_CHANNEL_M2M_OUT:
break;
#if DSL_DMA
case DMA_CHANNEL_DSL_TX : /* 5 */
if (DSLInfo.bTXWA)
{
if ( (DSLInfo.TxPendingInc != 0) && (DSLInfo.bTxSendMode == FALSE) )
{
DSLInfo.TxTotalPending += DSLInfo.TxPendingInc;
*pDSL_TXCC_DMA = DSLInfo.TxPendingInc; /* # of TX block to be sent */
DSLInfo.TxPendingInc = 0;
DSLInfo.bTxSendMode = TRUE;
bReturn = TRUE;
}
}
else if (DSLInfo.TxPendingInc)
{
DSLInfo.TxTotalPending += DSLInfo.TxPendingInc;
*pDSL_TXCC_DMA = DSLInfo.TxPendingInc; /* # of TX block to be sent */
DSLInfo.TxPendingInc = 0;
DSLInfo.bTxSendMode = TRUE;
bReturn = TRUE;
}
break;
case DMA_CHANNEL_DSL_RX :
#endif
case DMA_CHANNEL_EMAC1_TX :
case DMA_CHANNEL_EMAC2_TX :
case DMA_CHANNEL_EMAC1_RX :
case DMA_CHANNEL_EMAC2_RX :
default :
break;
}
INTUNLOCK(OldLevel);
return bReturn;
}
