//-------------------------------------------------------------------------------------------------
/// clear Interrupt
/// @param s32Fiq \b IN: interrupt number
/// @return E_MBX_SUCCESS: success;
/// @attention
/// <b>[MXLIB] <em></em></b>
//-------------------------------------------------------------------------------------------------
MBX_Result MHAL_MBXINT_Clear (MS_S32 s32Fiq)
{
MS_U16 u16RegValHost;
MS_U16 u16FIQMask;
MS_U16 u16IdxHost;
switch(s32Fiq)
{
case MBX_INT_MIPS2PM:
u16IdxHost = REG_INT_FIQMASK_PM;
u16FIQMask = _BIT_MIPS_PM;
break;
case MBX_INT_PM2MIPS:
u16IdxHost = REG_INT_FIQMASK_MIPS;
u16FIQMask = _BIT_PM_MIPS;
break;
case MBX_INT_AEON2MIPS:
u16IdxHost = REG_INT_FIQLMASK_MIPS;
u16FIQMask = _BIT_FRCR2_MIPS;
break;
default:
return 0;
}
mb();
u16RegValHost = INT_REG(u16IdxHost);
INT_REG(u16IdxHost) = u16RegValHost | (u16FIQMask);
mb();
return E_MBX_SUCCESS;
}
//-------------------------------------------------------------------------------------------------
/// enable/disable Interrupt
/// @param s32Fiq \b IN: interrupt for enable/disable
/// @param bEnable \b IN: Enable or Disable
/// @return E_MBX_SUCCESS: success;
/// @attention
/// <b>[OBAMA] <em></em></b>
//-------------------------------------------------------------------------------------------------
MBX_Result MHAL_MBXINT_Enable (MS_S32 s32Fiq, MS_BOOL bEnable)
{
MS_U16 u16RegValHost;
MS_U16 u16FIQMask;
MS_U16 u16IdxHost;
switch(s32Fiq)
{
case MBX_INT_MIPS2PM:
u16IdxHost = REG_INT_FIQMASK_PM;
u16FIQMask = _BIT_ARM_PM;
break;
case MBX_INT_PM2MIPS:
u16IdxHost = REG_INT_FIQMASK_ARM;
u16FIQMask = _BIT_PM_ARM;
break;
default:
return 0;
}
mb();
u16RegValHost = INT_REG(u16IdxHost);
if(bEnable)
{
INT_REG(u16IdxHost) = u16RegValHost & ~(u16FIQMask);
}
else
{
INT_REG(u16IdxHost) = u16RegValHost | (u16FIQMask);
}
mb();
return E_MBX_SUCCESS;
}
/**
* @brief Initialize CuRT Timer
*
* Once OS Timer is initialized, the timer is about to work.
* Note: the multi-tasking environment (setup by start_curt) will be invoked
* after this routine.
*/
void init_os_timer()
{
INT_REG(INT_ICLR) &= ~BIT26;
TMR_REG(TMR_OSMR0) = PXA255_TMR_CLK / OS_TICKS_PER_SEC;
TMR_REG(TMR_OSMR1) = 0x3FFFFFFF;
TMR_REG(TMR_OSMR2) = 0x7FFFFFFF;
TMR_REG(TMR_OSMR3) = 0xBFFFFFFF;
TMR_REG(TMR_OSCR) = 0x00;
TMR_REG(TMR_OSSR) = BIT0;
TMR_REG(TMR_OIER) = BIT0;
INT_REG(INT_ICMR) |= BIT26;
}
/**
* @brief Interrupt handler
*
* This function is invoked in the IRQ service routine.
* source: when calling advance_time_tick, ticks advance.
*/
void interrupt_handler()
{
if (INT_REG(INT_ICIP) & BIT26) {
TMR_REG(TMR_OSCR) = 0x00;
advance_time_tick();
TMR_REG(TMR_OSSR) = BIT0;
}
}
//-------------------------------------------------------------------------------------------------
/// Fire Interrupt
/// @param dstCPUID \b IN: dst cpu of interrupt
/// @param srcCPUID \b IN: src cpu of interrupt
/// @return E_MBX_SUCCESS: success;
/// @attention
/// <b>[OBAMA] <em></em></b>
//-------------------------------------------------------------------------------------------------
MBX_Result MHAL_MBXINT_Fire (MBX_CPU_ID dstCPUID, MBX_CPU_ID srcCPUID)
{
MBXINT_ASSERT((dstCPUID!=srcCPUID),"dst cpu is the same as src cpu!\n");
switch(srcCPUID)
{
case E_MBX_CPU_PM:
if(dstCPUID==E_MBX_CPU_AEON)
{
INT_REG(REG_INT_PMFIRE) = INT_PM2AEON;
}
else
{
INT_REG(REG_INT_PMFIRE) = INT_PM2MIPS;
}
mb();
INT_REG(REG_INT_PMFIRE) = 0;
mb();
break;
case E_MBX_CPU_AEON:
if(dstCPUID==E_MBX_CPU_PM)
{
INT_REG(REG_INT_AEONFIRE) = INT_AEON2PM;
}
else
{
INT_REG(REG_INT_AEONFIRE) = INT_AEON2MIPS;
}
mb();
INT_REG(REG_INT_AEONFIRE) = 0;
mb();
break;
case E_MBX_CPU_MIPS:
if(dstCPUID==E_MBX_CPU_PM)
{
AEON1_INT_REG(REG_INT_MIPSFIRE) = INT_MIPS2PM;
}
else
{
AEON1_INT_REG(REG_INT_MIPSFIRE) = INT_MIPS2AEON;
}
mb();
AEON1_INT_REG(REG_INT_MIPSFIRE) = 0;
mb();
break;
default:
MBXINT_ASSERT(FALSE,"wrong src cpu!\n");
break;
}
return E_MBX_SUCCESS;
}
/**
* @brief Initialize CPU interrupt control
*
* Enable the issue of interrupts.
*/
void init_interrupt_control()
{
INT_REG(INT_ICMR) = 0;
}